Gain Kim

Orcid: 0000-0002-3680-8816

According to our database1, Gain Kim authored at least 25 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Compact Single-Ended Transceivers Demonstrating Flexible Generation of 1/N-Rate Receiver Front-Ends for Short-Reach Links.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024

A Study on the Effects of Power Loading Profile in Discrete Multitone Wireline Serial-Data Transceiver with Fixed-Point DSP-SerDes Simulator.
Proceedings of the International Conference on Electronics, Information, and Communication, 2024

Area Optimization of the Feed-Forward Equalizer for ADC-Based High-Speed Wireline Receiver Using Channel Characteristics.
Proceedings of the International Conference on Electronics, Information, and Communication, 2024

2023
Far-End Crosstalk Cancellation With MIMO OFDM for >200 Gb/s ADC-Based Serial Links.
IEEE Trans. Circuits Syst. II Express Briefs, 2023

A 1V-Supply $1.85\mathrm{V}_{\text{PP}}$ -Input-Range 1kHz-BW 181.9dB-FOMDR179.4dB-FOMSNDR 2<sup>nd</sup>-Order Noise-Shaping SAR-ADC with Enhanced Input Impedance in 0.18μm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

An 86.71875GHz RF transceiver for 57.8125Gb/s waveguide links with a CDR-assisted carrier synchronization loop in 28nm.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

Does Charge Balancing Ensure the Safety of the Electrical Stimulation and Is It Power Efficientƒ.
Proceedings of the 45th Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2023

2022
Design Space Exploration of Single-Lane OFDM-Based Serial Links for High-Speed Wireline Communications.
IEEE Open J. Circuits Syst., 2022

Bin-Specific Quantization in Spectral-Domain Convolutional Neural Network Accelerators.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021
Link Bit-Error-Rate Requirement Analysis for Deep Neural Network Accelerators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET.
IEEE J. Solid State Circuits, 2020

2019
Design Considerations and Performance Trade-Offs for 56Gb/s Discrete Multi-Tone Electrical Link.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
Direct Reconstruction of Saturated Samples in Band-Limited OFDM Signals.
CoRR, 2018

Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
A Time-Division Multiplexing Signaling Scheme for Inter-Symbol/Channel Interference Reduction in Low-Power Multi-Drop Memory Links.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Design and Modeling of Serial Data Transceiver Architecture by Employing Multi-Tone Single-Sideband Signaling Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

2016
A Study on the Programming Structures for RRAM-Based FPGA Architectures.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A Digital Spectrum Shaping Signaling Serial-Data Transceiver With Crosstalk and ISI Reduction Property in Multidrop Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A fully-digital spectrum shaping signaling for serial-data transceiver with crosstalk and ISI reduction property in multi-drop memory interfaces.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Architectural modeling of a multi-tone/single-sideband serial link transceiver for lossy wireline data links.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
A Novel FPGA Architecture Based on Ultrafine Grain Reconfigurable Logic Cells.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Design optimization of polyphase digital down converters for extremely high frequency wireless communications.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015


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