Jiongzhe Su
Orcid: 0009-0005-4310-9246
According to our database1,
Jiongzhe Su authored at least 8 papers
between 2023 and 2026.
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Bibliography
2026
IEEE Trans. Reliab., 2026
A Highly-Scalable and Full-Connected SOT P-Bit Ising Annealer for Combinatorial Optimization.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
Non-volatile Spintronic Flip-Flops with Checkpoint Preservation Supported in RISC-V Platform.
Proceedings of the Design, Automation & Test in Europe Conference, 2026
A 28-nm Density-Capable 6ns Access Time MRAM Macro using Multi-bit Sense Amplifier and Dual-mode ECC.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026
2025
A 40nm 4Mb High-Reliability STT-MRAM Achieving 18ns Write-Time and 94.9% Wafer-Level-Die-Yield Across -55°C-to-125°C.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
2024
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2024
2023
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
Proceedings of the IEEE International Conference on Integrated Circuits, 2023