Bo Liu

According to our database, Bo Liu authored at least 69 papers between 2012 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

VoAD: A Sub-μW Multiscene Voice Activity Detector Deploying Analog-Frontend Digital-Backend Circuits.

Yu Gong, Bo Liu, Hao Cai, Longxing Shi, Weiqiang Liu

IEEE Trans. Circuits Syst. II Express Briefs, February, 2024

Sparsity-Oriented MRAM-Centric Computing for Efficient Neural Network Inference.

Jia-Le Cui, Yanan Guo, Juntong Chen, Bo Liu, Hao Cai

IEEE Trans. Emerg. Top. Comput., 2024

2023

W-AMA: Weight-aware Approximate Multiplication Architecture for neural processing.

Bo Liu, Renyuan Zhang, Qiao Shen, Zeju Li, Na Xie, Yuanhao Wang, Chonghang Xie, Hao Cai

Comput. Electr. Eng., October, 2023

Computing in-memory with cascaded spintronic devices for AI edge.

Zhong-Jian Bian, Bo Liu, Hao Cai

Comput. Electr. Eng., August, 2023

Multiplication Circuit Architecture for Error- Tolerant CNN-Based Keywords Speech Recognition.

Bo Liu, Hao Cai, Zilong Zhang, Xiaoling Ding, Renyuan Zhang, Yu Gong, Zhen Wang, Wei Ge, Jun Yang

IEEE Des. Test, June, 2023

Dependable STT-MRAM With Emerging Approximation and Speculation Paradigms.

Hao Cai, Yaoru Hou, Mengdi Zhang, Bo Liu, Lirida Alves de Barros Naviner

IEEE Des. Test, June, 2023

A Reconfigurable Approximate Computing Architecture With Dual-VDD for Low-Power Binarized Weight Network Deployment.

Bo Liu, Anfeng Xue, Ziyu Wang, Na Xie, Xuetao Wang, Zhen Wang, Hao Cai

IEEE Trans. Circuits Syst. II Express Briefs, 2023

A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference.

Hao Cai, Zhong-Jian Bian, Yaoru Hou, Yongliang Zhou, Jia-Le Cui, Yanan Guo, Xiaoyun Tian, Bo Liu, Xin Si, Zhen Wang, Jun Yang, Weiwei Shan

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

Work-in-Process: Error-Compensation-Based Energy-Efficient MAC Unit for CNNs.

Xingyu Xu, Qingwen Wei, Yang Zhang, Hao Cai, Bo Liu

Proceedings of the International Conference on Compilers, 2023

2022

Writing-only in-MRAM computing paradigm for ultra-low power applications.

Bo Liu, Mingyue Liu, Yongliang Zhou, Xiaofeng Hong, Hao Cai, Lirida Alves de Barros Naviner

Microprocess. Microsystems, April, 2022

More is Less: Domain-Specific Speech Recognition Microprocessor Using One-Dimensional Convolutional Recurrent Neural Network.

Bo Liu, Hao Cai, Zilong Zhang, Xiaoling Ding, Ziyu Wang, Yu Gong, Weiqiang Liu, Jinjiang Yang, Zhen Wang, Jun Yang

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Quality Driven Systematic Approximation for Binary-Weight Neural Network Deployment.

Yu Gong, Hao Cai, Haige Wu, Wei Ge, Hao Yan, Zhen Wang, Longxing Shi, Bo Liu

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Proposal of Analog In-Memory Computing With Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell.

Hao Cai, Yanan Guo, Bo Liu, Mingyang Zhou, Juntong Chen, Xinning Liu, Jun Yang

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

An Efficient BCNN Deployment Method Using Quality-Aware Approximate Computing.

Bo Liu, Ziyu Wang, Xuetao Wang, Renyuan Zhang, Anfeng Xue, Qiao Shen, Na Xie, Yu Gong, Zhen Wang, Jun Yang, Hao Cai

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Self-compensation tensor multiplication unit for adaptive approximate computing in low-power CNN processing.

Bo Liu, Zilong Zhang, Hao Cai, Reyuan Zhang, Zhen Wang, Jun Yang

Sci. China Inf. Sci., 2022

Background Noise Adaptive Energy-Efficient Keywords Recognition Processor With Reusable DNN and Reconfigurable Architecture.

Guoqiang He, Xiaoling Ding, Minghao Zhou, Bo Liu, Li Li

IEEE Access, 2022

A Low Power DNN-based Speech Recognition Processor with Precision Recoverable Approximate Computing.

Bo Liu, Xuetao Wang, Renyuan Zhang, Anfeng Xue, Ziyu Wang, Haige Wu, Hao Cai

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A TWN Inspired Speaker Verification Processor with Hardware-friendly Weight Quantization.

Xuanhao Zhang, Haige Wu, Renyuan Zhang, Zihang Xu, Hao Zhang, Bo Liu, Hao Cai

Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

A CGP-based Efficient Approximate Multiplier with Error Compensation.

Qiao Shen, Renyuan Zhang, Hao Zhang, Hao Cai, Bo Liu, Jian Xiao

Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

A Target-Separable BWN Inspired Speech Recognition Processor with Low-power Precision-adaptive Approximate Computing.

Bo Liu, Hao Cai, Xuan Zhang, Haige Wu, Anfeng Xue, Zilong Zhang, Zhen Wang, Jun Yang

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Triple-Skipping Near-MRAM Computing Framework for AIoT Era.

Juntong Chen, Hao Cai, Bo Liu, Jun Yang

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

A survey of in-spin transfer torque MRAM computing.

Hao Cai, Bo Liu, Juntong Chen, Lirida A. B. Naviner, Yongliang Zhou, Zhen Wang, Jun Yang

Sci. China Inf. Sci., 2021

Reconfigurable Approximate Multiplication Architecture for CNN-Based Speech Recognition Using Wallace Tree Tensor Multiplier Unit.

Junyi Qian, Yuanyuan Jiang, Zilong Zhang, Renyuan Zhang, Ziyu Wang, Bo Liu

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021

Cryogenic In-MRAM Computing.

Yaoru Hou, We Ge, Yanan Guo, Lirida A. B. Naviner, You Wang, Bo Liu, Jun Yang, Hao Cai

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021

In-MRAM Computing Elements with Single-Step Convolution and Fully Connected for BNN/TNN.

Zhong-Jian Bian, Yanan Guo, Bo Liu, Hao Cai

Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

A 1D-CRNN Inspired Reconfigurable Processor for Noise-robust Low-power Keywords Recognition.

Bo Liu, Zeyu Shen, Lepeng Huang, Yu Gong, Zilong Zhang, Hao Cai

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Low-Power Keyword Recognition Feature Extraction Circuit based on SRMFCC and Shared Multiplier for High Noise Background.

Zilong Zhang, Haichuang Yang, Xuan Zhang, Xiaoling Ding, Xuetao Wang, Yu Gong, Bo Liu

Proceedings of the 14th IEEE International Conference on ASIC, 2021

Mutual Error Compensation based Area and Power efficient Approximate Multiplier.

Renyuan Zhang, Xuetao Wang, Ziyu Wang, Anfeng Xue, Haichuan Yang, Yu Gong, Bo Liu

Proceedings of the 14th IEEE International Conference on ASIC, 2021

An Always-on Ultra-Low Power Speaker Verification Accelerator based on Binary Weighted Neural Network with System Co-optimization.

Haige Wu, Xuan Zhang, Xiaoling Ding, Ziyu Wang, Anfeng Xue, Yu Gong, Bo Liu

Proceedings of the 14th IEEE International Conference on ASIC, 2021

Implementation of a CRNN-based low-power keyword recognition system on FPGA.

Limo Guo, PengXu Lin, Lei Guo, Bo Liu

Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020

A Self-Timed Voltage-Mode Sensing Scheme With Successive Sensing and Checking for STT-MRAM.

Yongliang Zhou, Hao Cai, Lei Xie, Menglin Han, Mingyue Liu, Shi Xu, Bo Liu, Weisheng Zhao, Jun Yang

IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

MTJ-LRB: Proposal of MTJ-Based Loop Replica Bitline as MRAM Device-Circuit Interaction for PVT-Robust Sensing.

Yongliang Zhou, Hao Cai, Bo Liu, Weisheng Zhao, Jun Yang

IEEE Trans. Circuits Syst., 2020

A 22nm, 10.8 μ W/15.1 μ W Dual Computing Modes High Power-Performance-Area Efficiency Domained Background Noise Aware Keyword- Spotting Processor.

Bo Liu, Hao Cai, Zhen Wang, Yuhao Sun, Zeyu Shen, Wentao Zhu, Yan Li, Yu Gong, Wei Ge, Jun Yang, Longxing Shi

IEEE Trans. Circuits Syst., 2020

A Power Analysis Attack Countermeasure Based on Random Data Path Execution For CGRA.

Wei Ge, Shenghua Chen, Benyu Liu, Min Zhu, Bo Liu

IEICE Trans. Inf. Syst., 2020

FPGA implementation of a challenge pre-processing structure arbiter PUF designed for machine learning attack resistance.

Wei Ge, Shenxin Hu, Ji Quan Huang, Bo Liu, Min Zhu

IEICE Electron. Express, 2020

Interplay Bitwise Operation in Emerging MRAM for Efficient In-memory Computing.

Hao Cai, Honglan Jiang, Yongliang Zhou, Menglin Han, Bo Liu

CCF Trans. High Perform. Comput., 2020

QCNN Inspired Reconfigurable Keyword Spotting Processor With Hybrid Data-Weight Reuse Methods.

Yu Gong, Yan Li, Xiaoling Ding, Haichuan Yang, Zilong Zhang, Xuan Zhang, Wei Ge, Zhen Wang, Bo Liu

IEEE Access, 2020

Binarized Weight Neural-Network Inspired Ultra-Low Power Speech Recognition Processor with Time-Domain Based Digital-Analog Mixed Approximate Computing.

Bo Liu, Hao Cai, Yu Gong, Wentao Zhu, Yan Li, Wei Ge, Zhen Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A High-throughput Low-area Entropy Source Based on Asynchronous Feedback Unit.

Ping Wang, Jinjiang Yang, Min Zhu, Bo Liu

Proceedings of the ICCSP 2020: 4th International Conference on Cryptography, 2020

A Background Noise Self-adaptive VAD Using SNR Prediction Based Precision Dynamic Reconfigurable Approximate Computing.

Bo Liu, Yan Li, Lepeng Huang, Hao Cai, Wentao Zhu, Shisheng Guo, Yu Gong, Zhen Wang

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

An Ultra-low Power Keyword-Spotting Accelerator Using Circuit-Architecture-System Co-design and Self-adaptive Approximate Computing Based BWN.

Bo Liu, Yuhao Sun, Hao Cai, Zeyu Shen, Yu Gong, Lepeng Huang, Zhen Wang

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

2019

An energy-efficient voice activity detector using deep neural networks and approximate computing.

Bo Liu, Zhen Wang, Shisheng Guo, Huazhen Yu, Yu Gong, Jun Yang, Longxing Shi

Microelectron. J., 2019

ARA: Cross-Layer approximate computing framework based reconfigurable architecture for CNNs.

Yu Gong, Bo Liu, Wei Ge, Longxing Shi

Microelectron. J., 2019

An Ultra-Low Power Always-On Keyword Spotting Accelerator Using Quantized Convolutional Neural Network and Voltage-Domain Analog Switching Network-Based Approximate Computing.

Bo Liu, Zhen Wang, Wentao Zhu, Yuhao Sun, Zeyu Shen, Lepeng Huang, Yan Li, Yu Gong, Wei Ge

IEEE Access, 2019

EERA-KWS: A 163 TOPS/W Always-on Keyword Spotting Accelerator in 28nm CMOS Using Binary Weight Network and Precision Self-Adaptive Approximate Computing.

Bo Liu, Zhen Wang, Hu Fan, Jing Yang, Bo Liu, Wentao Zhu, Lepeng Huang, Yu Gong, Wei Ge, Longxing Shi

IEEE Access, 2019

A Self-Timing Voltage-Mode Sense Amplifier for STT-MRAM Sensing Yield Improvement.

Yongliang Zhou, Menglin Han, Mingyue Liu, Hao Cai, Bo Liu, Jun Yang

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

2018

A Double Dwell High Sensitivity GPS Acquisition Scheme Using Binarized Convolution Neural Network.

Zhen Wang, Yuan Zhuang, Jun Yang, Hengfeng Zhang, Wei Dong, Min Wang, Luchi Hua, Bo Liu, Longxing Shi

Sensors, 2018

EERA-DNN: An energy-efficient reconfigurable architecture for DNNs with hybrid bit-width and logarithmic multiplier.

Zhen Wang, Mengwen Xia, Bo Liu, Xing Ruan, Yu Gong, Jinjiang Yang, Wei Ge, Jun Yang

IEICE Electron. Express, 2018

EERA-ASR: An Energy-Efficient Reconfigurable Architecture for Automatic Speech Recognition With Hybrid DNN and Approximate Computing.

Bo Liu, Hai Qin, Yu Gong, Wei Ge, Mengwen Xia, Longxing Shi

IEEE Access, 2018

A Power Analysis Attack Countermeasure Based on Random Execution.

Shenghua Chen, Wei Ge, Jinjiang Yang, Bo Liu, Jun Yang

Proceedings of the 17th IEEE International Conference On Trust, 2018

An Energy-efficient Reconfigurable Hybrid DNN Architecture for Speech Recognition with Approximate Computing.

Bo Liu, Shisheng Guo, Hai Qin, Yu Gong, Jinjiang Yang, Wei Ge, Jun Yang

Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

Design and Optimization of Reconfigurable Data Path for Communication Baseband Signal Processing.

Shan-shan Zhu, Hai Qin, Bo Liu, Jun Yang

Proceedings of the International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, 2018

A Deep Learning Modeling Attack Method for MISR-APUF Protection Structures.

Wei Ge, Ji Quan Huang, Bo Liu, Min Zhu, Yuan Cao

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017

Context Management Scheme Optimization of Coarse-Grained Reconfigurable Architecture for Multimedia Applications.

Peng Cao, Bo Liu, Jinjiang Yang, Jun Yang, Meng Zhang, Longxing Shi

IEEE Trans. Very Large Scale Integr. Syst., 2017

Coarse-grained reconfigurable architecture with hierarchical context cache structure and management approach.

Chao Wang, Peng Cao, Bo Liu, Jun Yang

IEICE Electron. Express, 2017

E-ERA: An energy-efficient reconfigurable architecture for RNNs using dynamically adaptive approximate computing.

Bo Liu, Wei Dong, Tingting Xu, Yu Gong, Wei Ge, Jinjiang Yang, Longxing Shi

IEICE Electron. Express, 2017

An energy-efficient accelerator for hybrid bit-width DNNs.

Bo Liu, Xing Ruan, Mengwen Xia, Yu Gong, Jinjiang Yang, Wei Ge, Jun Yang

Proceedings of the 2017 IEEE Symposium Series on Computational Intelligence, 2017

Processing LSTM in memory using hybrid network expansion model.

Yu Gong, Tingting Xu, Bo Liu, Wei Ge, Jinjiang Yang, Jun Yang, Longxing Shi

Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

Implementation and Verification of a High-Throughput Reconfigurable MIMO Detector.

Zhen Wang, Hai Qin, Yu Gong, Bo Liu

Proceedings of the 2017 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, 2017

2016

A Novel Design of Pipeline MDC-FFT Processor Based on Various Memory Access Mechanism.

Jinjiang Yang, Dongming Zhang, Yu Gong, Bo Liu

Proceedings of the International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, 2016

2015

Performance-Conscious Reconfiguration Structure for Large-Scale Coarse-Grained Reconfigurable System.

Bo Liu, Yu Gong, Rui-he Wang, Yang Liu

Proceedings of the 2015 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, 2015

A novel routing structure of coarse-grained reconfigurable architecture for radar application.

Bo Liu, Dongming Zhang, Wei-qi Ge, Yu Gong

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A novel configuration context cache structure of reconfigurable systems.

Yu Gong, Bo Liu, Chen Mei, Rui-he Wang

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014

Hierarchical Pipeline Optimization of Coarse Grained Reconfigurable Processor for Multimedia Applications.

Chen Mei, Peng Cao, Yang Zhang, Bo Liu, Leibo Liu

Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

A Configuration Compression Approach for Coarse-Grain Reconfigurable Architecture for Radar Signal Processing.

Bo Liu, Wan-Yu Zhu, Yang Liu, Peng Cao

Proceedings of the 2014 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, 2014

2012

Reconfiguration Process Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications.

Bo Liu, Peng Cao, Min Zhu, Jun Yang, Leibo Liu, Shaojun Wei, Longxing Shi

IEICE Trans. Inf. Syst., 2012

Hybrid-Priority Configuration Cache Supervision Method for Coarse Grained Reconfigurable Architecture.

Bo Liu, Peng Cao, Jinjiang Yang

Proceedings of the 2012 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, 2012

Memory Bandwidth Optimization Strategy of Coarse-Grained Reconfigurable Architecture.

Peng Cao, Huiyan Jiang, Bo Liu, Weiwei Shan

Proceedings of the 2012 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, 2012

Configuration Cache Management for Coarse-Grained Reconfigurable Architecture with Multi-Array.

Peng Cao, Yong Cai, Bo Liu, Weiwei Shan

Proceedings of the 2012 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, 2012