Jun Yang
Orcid: 0000-0002-8379-0321Affiliations:
- Southeast University, National ASIC system Engineering Research Center, Nanjing, China
According to our database1,
Jun Yang
authored at least 141 papers
between 2005 and 2024.
Collaborative distances:
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Bibliography
2024
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
High-Performance Placement Engine for Modern Large-Scale FPGAs With Heterogeneity and Clock Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2024
A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-Voltage Multivoltage/ Frequency-Domain Network-on-Chip.
IEEE J. Solid State Circuits, February, 2024
TICA: Timing Slack Inference and Clock Frequency Adaption Technique for a Deeply Pipelined Near-Threshold-Voltage Bitcoin Mining Core.
IEEE J. Solid State Circuits, February, 2024
An Effective Routing Refinement Algorithm Based on Incremental Replacement and Rerouting.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024
14.2 Proactive Voltage Droop Mitigation Using Dual-Proportional-Derivative Control Based on Current and Voltage Prediction Applied to a Multicore Processor in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
Triplet MatchNet Based Indoor Position Method Using CSI Fingerprint Similarity Comparison.
IEEE Trans. Veh. Technol., December, 2023
From macro to microarchitecture: reviews and trends of SRAM-based compute-in-memory circuits.
Sci. China Inf. Sci., October, 2023
Efficient and Accurate ECO Leakage Optimization Framework With GNN and Bidirectional LSTM.
IEEE Trans. Very Large Scale Integr. Syst., September, 2023
Multi-sensor integrated navigation/positioning systems using data fusion: From analytics-based to learning-based approaches.
Inf. Fusion, July, 2023
A 0.55V 10-Bit 100-MS/s SAR ADC With 3.6-fJ/Conversion-Step in 28nm CMOS for RF Receivers.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023
Frontiers Neurorobotics, June, 2023
Multiplication Circuit Architecture for Error- Tolerant CNN-Based Keywords Speech Recognition.
IEEE Des. Test, June, 2023
Beyond Eliminating Timing Margin: An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator Without Accuracy Loss.
IEEE J. Solid State Circuits, May, 2023
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
AAD-KWS: A Sub-μ W Keyword Spotting Chip With an Acoustic Activity Detector Embedded in MFCC and a Tunable Detection Window in 28-nm CMOS.
IEEE J. Solid State Circuits, March, 2023
Sci. China Inf. Sci., February, 2023
An Ultra-Low-Voltage 2.4-GHz Flicker-Noise-Free RF Receiver Front End Based on Switched-Capacitor Hybrid TIA With 4.5-dB NF and 11.5-dBm OIP3.
IEEE J. Solid State Circuits, 2023
A 28nm Horizontal-Weight-Shift and Vertical-feature-Shift-Based Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
More is Less: Domain-Specific Speech Recognition Microprocessor Using One-Dimensional Convolutional Recurrent Neural Network.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Proposal of Analog In-Memory Computing With Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE J. Solid State Circuits, 2022
CoRR, 2022
Self-compensation tensor multiplication unit for adaptive approximate computing in low-power CNN processing.
Sci. China Inf. Sci., 2022
SNNIM: A 10T-SRAM based Spiking-Neural-Network-In-Memory architecture with capacitance computation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
ShareFloat CIM: A Compute-In-Memory Architecture with Floating-Point Multiply-and-Accumulate Operations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A 28nm, 4.69TOPS/W Training, 2.34µJ/lmage Inference, on-chip Training Accelerator with Inference-compatible Back Propagation.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022
Graph Convolutional Network Empowered Indoor Localization Method via Aggregating MIMO CSI.
Proceedings of the IEEE Global Communications Conference, 2022
A Target-Separable BWN Inspired Speech Recognition Processor with Low-power Precision-adaptive Approximate Computing.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
MPAM: Reliable, Low-Latency, Near-Threshold-Voltage Multi-Voltage/Frequency-Domain Network-on-Chip with Metastability Risk Prediction and Mitigation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
TICA: A 0.3V, Variation-Resilient 64-Stage Deeply-Pipelined Bitcoin Mining Core with Timing Slack Inference and Clock Frequency Adaption.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
IEEE Trans. Veh. Technol., 2021
A Design of Timing Speculation SRAM-Based L1 Caches With PVT Autotracking Under Near-Threshold Voltages.
IEEE Trans. Very Large Scale Integr. Syst., 2021
Semi-Analytical Path Delay Variation Model With Adjacent Gates Decorrelation for Subthreshold Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
TIMAQ: A Time-Domain Computing-in-Memory-Based Processor Using Predictable Decomposed Convolution for Arbitrary Quantized DNNs.
IEEE J. Solid State Circuits, 2021
A 510-nW Wake-Up Keyword-Spotting Chip Using Serial-FFT-Based MFCC and Binarized Depthwise Separable CNN in 28-nm CMOS.
IEEE J. Solid State Circuits, 2021
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021
29.8 115nA@3V ULPMark-CP Score 1205 SCVR-Less Dynamic Voltage-Stacking Scheme for IoT MCU.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Design Methodology towards High-Precision SRAM based Computation-in-Memory for AI Edge Devices.
Proceedings of the 18th International SoC Design Conference, 2021
An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator without Accuracy Loss in 28nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
A Self-Timed Voltage-Mode Sensing Scheme With Successive Sensing and Checking for STT-MRAM.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020
MTJ-LRB: Proposal of MTJ-Based Loop Replica Bitline as MRAM Device-Circuit Interaction for PVT-Robust Sensing.
IEEE Trans. Circuits Syst., 2020
A 22nm, 10.8 μ W/15.1 μ W Dual Computing Modes High Power-Performance-Area Efficiency Domained Background Noise Aware Keyword- Spotting Processor.
IEEE Trans. Circuits Syst., 2020
Bandwidth-Enhanced Oversampling Successive Approximation Readout Technique for Low-Noise Power-Efficient MEMS Capacitive Accelerometer.
IEEE J. Solid State Circuits, 2020
Machine Learning Assisted Side-Channel-Attack Countermeasure and Its Application on a 28-nm AES Circuit.
IEEE J. Solid State Circuits, 2020
TG-SPP: A One-Transmission-Gate Short-Path Padding for Wide-Voltage-Range Resilient Circuits in 28-nm CMOS.
IEEE J. Solid State Circuits, 2020
A Bi-Directional, Zero-Latency Adaptive Clocking Circuit in a 28-nm Wide AVFS System.
IEEE J. Solid State Circuits, 2020
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
14.1 A 510nW 0.41V Low-Memory Low-Computation Keyword-Spotting Chip Using Serial FFT-Based MFCC and Binarized Depthwise Separable Convolutional Neural Network in 28nm CMOS.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Statistical Timing Model for Subthreshold Circuit with Correlated Variation Consideration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
A Time-Domain Computing-in-Memory based Processor using Predictable Decomposed Convolution for Arbitrary Quantized DNNs.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020
2019
IEEE Trans. Veh. Technol., 2019
A Wide-Voltage-Range Half-Path Timing Error-Detection System With a 9-Transistor Transition-Detector in 40-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
The Integration of Photodiode and Camera for Visible Light Positioning by Using Fixed-Lag Ensemble Kalman Smoother.
Remote. Sens., 2019
An energy-efficient voice activity detector using deep neural networks and approximate computing.
Microelectron. J., 2019
Low-Power Centimeter-Level Localization for Indoor Mobile Robots Based on Ensemble Kalman Smoother Using Received Signal Strength.
IEEE Internet Things J., 2019
Lowering the Hit Latencies of Low Voltage Caches Based on the Cross-Sensing Timing Speculation SRAM.
IEEE Access, 2019
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Nonlinear Functions in Learned Iterative Shrinkage-Thresholding Algorithm for Sparse Signal Recovery.
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019
Accurate and Efficient Interdependent Timing Model for Flip-Flop in Wide Voltage Region.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
REAL: Logic and Arithmetic Operations Embedded in RRAM for General-Purpose Computing.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
RRS cache: a low voltage cache based on timing speculation SRAM with a reuse-aware cacheline remapping mechanism.
Proceedings of the International Symposium on Memory Systems, 2019
Pj-AxMTJ: Process-in-memory with Joint Magnetization Switching for Approximate Computing in Magnetic Tunnel Junction.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Sandwich-RAM: An Energy-Efficient In-Memory BWN Architecture with Pulse-Width Modulation.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the 11th International Symposium on Image and Signal Processing and Analysis, 2019
Proceedings of the International Conference on Computer-Aided Design, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Voltage-Controlled Magnetoelectric Memory Bit-cell Design With Assisted Body-bias in FD-SOI.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
A Statistical Current and Delay Model Based on Log-Skew-Normal Distribution for Low Voltage Region.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
2018
A Low Overhead, Within-a-Cycle Adaptive Clock Stretching Circuit With Wide Operating Range in 40-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Timing Error Prediction AVFS With Detection Window Tuning for Wide-Operating-Range ICs.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
HTD: A Light-Weight Holosymmetrical Transition Detector for Wide-Voltage-Range Variation Resilient ICs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A Double Dwell High Sensitivity GPS Acquisition Scheme Using Binarized Convolution Neural Network.
Sensors, 2018
A Double Sensing Scheme With Selective Bitline Voltage Regulation for Ultralow-Voltage Timing Speculative SRAM.
IEEE J. Solid State Circuits, 2018
A Pervasive Integration Platform of Low-Cost MEMS Sensors and Wireless Signals for Indoor Localization.
IEEE Internet Things J., 2018
Guest Editorial: Special Issue on Toward Positioning, Navigation, and Location-Based Services (PNLBS) for Internet of Things.
IEEE Internet Things J., 2018
EERA-DNN: An energy-efficient reconfigurable architecture for DNNs with hybrid bit-width and logarithmic multiplier.
IEICE Electron. Express, 2018
IEICE Electron. Express, 2018
IEEE Commun. Surv. Tutorials, 2018
A Low-Overhead Timing Monitoring Technique for Variation-Tolerant Near-Threshold Digital Integrated Circuits.
IEEE Access, 2018
IEEE Access, 2018
Proceedings of the 17th IEEE International Conference On Trust, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
An Energy-efficient Reconfigurable Hybrid DNN Architecture for Speech Recognition with Approximate Computing.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018
A fast and robust failure analysis of memory circuits using adaptive importance sampling method.
Proceedings of the 55th Annual Design Automation Conference, 2018
Design and Optimization of Reconfigurable Data Path for Communication Baseband Signal Processing.
Proceedings of the International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, 2018
A 0.46V-1.1V Transition-Detector with In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in AES Accelerator.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
Stability and Variability Emphasized STT-MRAM Sensing Circuit With Performance Enhancement.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
2017
Context Management Scheme Optimization of Coarse-Grained Reconfigurable Architecture for Multimedia Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Coarse-grained reconfigurable architecture with hierarchical context cache structure and management approach.
IEICE Electron. Express, 2017
IEICE Electron. Express, 2017
IEICE Electron. Express, 2017
Analytical inverter chain's delay and its variation model for sub-threshold circuits.
IEICE Electron. Express, 2017
In-Situ Timing Monitor-Based Adaptive Voltage Scaling System for Wide-Voltage-Range Applications.
IEEE Access, 2017
Proceedings of the 2017 IEEE Symposium Series on Computational Intelligence, 2017
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017
Analytical hold timing fixing for sub-threshold circuit based on its lognormal distribution.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017
A 0.44V-1.1V 9-transistor transition-detector and half-path error detection technique for low power applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
HTD: A light-weight holosymmetrical transition detector based in-situ timing monitoring technique for wide-voltage-range in 40nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
Sensors, 2016
An area-efficient design of reconfigurable S-box for parallel implementation of block ciphers.
IEICE Electron. Express, 2016
High performance and area efficiency design of global register file for coarse-grained reconfigurable cryptographic processor.
IEICE Electron. Express, 2016
2015
Correction to "An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding".
IEEE Trans. Multim., 2015
An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding.
IEEE Trans. Multim., 2015
IEICE Trans. Commun., 2015
2014
On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time.
IEEE Trans. Very Large Scale Integr. Syst., 2014
A Side-channel Analysis Resistant Reconfigurable Cryptographic Coprocessor Supporting Multiple Block Cipher Algorithms.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
Exploration of Full HD Media Decoding on a Software Defined Radio Baseband Processor.
IEEE Trans. Signal Process., 2013
Int. J. Inf. Commun. Technol., 2013
The Organization of On-Chip Data Memory in One Coarse-Grained Reconfigurable Architecture.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
Hardware Software Co-design of H.264 Baseline Encoder on Coarse-Grained Dynamically Reconfigurable Computing System-on-Chip.
IEICE Trans. Inf. Syst., 2013
Parallelism Analysis of H.264 Decoder and Realization on a Coarse-Grained Reconfigurable SoC.
IEICE Trans. Inf. Syst., 2013
IEICE Electron. Express, 2013
Hierarchical representation of on-chip context to reduce reconfiguration time and implementation area for coarse-grained reconfigurable architecture.
Sci. China Inf. Sci., 2013
2012
Fast AdaBoost-Based Face Detection System on a Dynamically Coarse Grain Reconfigurable Architecture.
IEICE Trans. Inf. Syst., 2012
Reconfiguration Process Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications.
IEICE Trans. Inf. Syst., 2012
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012
2011
A Fast Locking All-Digital Phase-Locked Loop via Feed-Forward Compensation Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2011
2009
Extended Control Flow Graph Based Performance and Energy Consumption Optimization Using Scratch-Pad Memory.
J. Circuits Syst. Comput., 2009
Area-efficient line-based two-dimensional discrete wavelet transform architecture without data buffer.
Proceedings of the 2009 IEEE International Conference on Multimedia and Expo, 2009
2008
IEICE Trans. Electron., 2008
2005
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005