Jiqing Xu

Orcid: 0000-0001-8177-7994

According to our database1, Jiqing Xu authored at least 9 papers between 2019 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
A dToF Ranging Sensor with Accurate Photon Detector Measurements for LiDAR Applications.
Sensors, March, 2023

Solid-State dToF LiDAR System Using an Eight-Channel Addressable, 20-W/Ch Transmitter, and a 128 × 128 SPAD Receiver With SNR-Based Pixel Binning and Resolution Upscaling.
IEEE J. Solid State Circuits, March, 2023

A Fully Integrated dToF System-on-Chip with High Precision Using Adaptive Optical Power Control and Shifted Histogram-Bin Binning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A 2KSPS 123dB Dynamic-Range SPAD-based Optical Sensor SoC with On-chip Auto-Gain-Control and FFT Processor for 100 μlux Light Illuminance and Flicker Detection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A 2GHz On-Chip-Oscilloscope with High Accuracy Pulse Width Detection for Auto-Peak-Power Controller & Peak-Current Detector in Voltage-Mode DToF Driver.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
An 8-A Sub-1ns Pulsed VCSEL Driver IC With Built-In Pulse Monitor and Automatic Peak Current Control for Direct Time-of-Flight Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Solid-State dToF LiDAR System Using an Eight-Channel Addressable, 20W/Ch Transmitter, and a 128x128 SPAD Receiver with SNR-Based Pixel Binning and Resolution Upscaling.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2019
Research on the impact of different benchmark circuits on the representative path in FPGAs.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

Research on Area Modeling Methodology for FPGA Interconnect Circuits.
Proceedings of the 13th IEEE International Conference on ASIC, 2019


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