Gang Qu

Affiliations:
  • University of Maryland, Department of Electrical and Computer Engineering, Institute for Systems Research, College Park, MD, USA
  • University of California at Los Angeles, CA, USA (PhD 2000)


According to our database1, Gang Qu authored at least 257 papers between 1998 and 2022.

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Bibliography

2022
RMLIM: A Runtime Machine Learning Based Identification Model for Approximate Computing on Data Flow Graphs.
IEEE Trans. Sustain. Comput., 2022

Double-Shift: A Low-Power DNN Weights Storage and Access Framework based on Approximate Decomposition and Quantization.
ACM Trans. Design Autom. Electr. Syst., 2022

Accelerating Graph-Connected Component Computation With Emerging Processing-In-Memory Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Voltage Over-Scaling-Based Lightweight Authentication for IoT Security.
IEEE Trans. Computers, 2022

Triangle Counting Accelerations: From Algorithm to In-Memory Computing Architecture.
IEEE Trans. Computers, 2022

AutoTEA: An Automated Transistor-level Efficient and Accurate design tool for FPGA design.
Integr., 2022

MES-Attacks: Software-Controlled Covert Channels based on Mutual Exclusion and Synchronization.
CoRR, 2022

PMUSpill: The Counters in Performance Monitor Unit that Leak SGX-Protected Secrets.
CoRR, 2022

Fooling the Eyes of Autonomous Vehicles: Robust Physical Adversarial Examples Against Traffic Sign Recognition Systems.
CoRR, 2022

Innovation Practices Track: Security in Test and Test for Security.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022

Building Hardware Security Primitives Using Scan-based Design-for-Testability.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

An Effective Test Method for Block RAMs in Heterogeneous FPGAs Based on a Novel Partial Bitstream Relocation Technique.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

A Memristor-based Secure Scan Design against the Scan-based Side-Channel Attacks.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

DA PUF: dual-state analog PUF.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

CacheGuard: A Behavior Model Checker for Cache Timing Side-Channel Security: (Invited Paper).
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

DVFSspy: Using Dynamic Voltage and Frequency Scaling as a Covert Channel for Multiple Procedures.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
VoltJockey: A New Dynamic Voltage Scaling-Based Fault Injection Attack on Intel SGX.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Who is Charging My Phone? Identifying Wireless Chargers via Fingerprinting.
IEEE Internet Things J., 2021

AoI-Minimal Trajectory Planning and Data Collection in UAV-Assisted Wireless Powered IoT Networks.
IEEE Internet Things J., 2021

Age-Aware Utility Maximization in Relay-Assisted Wireless Powered Communication Networks.
Entropy, 2021

Lightning: Striking the Secure Isolation on GPU Clouds with Transient Hardware Faults.
CoRR, 2021

Meta Federated Learning.
CoRR, 2021

EarArray: Defending against DolphinAttack via Acoustic Attenuation.
Proceedings of the 28th Annual Network and Distributed System Security Symposium, 2021

Don't Forget to Sign the Gradients!
Proceedings of Machine Learning and Systems 2021, 2021

Identification of Counter Registers through Full Scan Chain.
Proceedings of the IEEE International Test Conference in Asia, 2021

Novel Memristor-based Nonvolatile D Latch and Flip-flop Designs.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Provably Accurate Memory Fault Detection Method for Deep Neural Networks.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

AutoTEA: Automated Transistor-level Efficient and Accurate Optimization for GRM FPGA Design.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

FTApprox: A Fault-Tolerant Approximate Arithmetic Computing Data Format.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Invited: Independent Verification and Validation of Security-Aware EDA Tools and IP.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

AID: Attesting the Integrity of Deep Neural Networks.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Security of Neural Networks from Hardware Perspective: A Survey and Beyond.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

RIME: A Scalable and Energy-Efficient Processing-In-Memory Architecture for Floating-Point Operations.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

A Novel Circuit Authentication Scheme Based on Partial Polymorphic Gates.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2021

2020
Physical Unclonable Function-Based Key Sharing via Machine Learning for IoT Security.
IEEE Trans. Ind. Electron., 2020

Estimate and Recompute: A Novel Paradigm for Approximate Computing on Data Flow Graphs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Guaranteed Secure Scan Design Based on Test Data Obfuscation by Cryptographic Hash.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

VoltJockey: Abusing the Processor Voltage to Break Arm TrustZone.
GetMobile Mob. Comput. Commun., 2020

Security in Approximate Computing and Approximate Computing for Security: Challenges and Opportunities.
Proc. IEEE, 2020

Hardware Security in Spin-based Computing-in-memory: Analysis, Exploits, and Mitigation Techniques.
ACM J. Emerg. Technol. Comput. Syst., 2020

A New Secure Scan Design with PUF-based Key for Authentication.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020

A Low-Cost Fault Injection Attack Resilient FSM Design.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

Efficient Transfer Learning on Modeling Physical Unclonable Functions.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Impacts of Machine Learning on Counterfeit IC Detection and Avoidance Techniques.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

MagView: A Distributed Magnetic Covert Channel via Video Encoding and Decoding.
Proceedings of the 39th IEEE Conference on Computer Communications, 2020

A New Aging Sensor for the Detection of Recycled ICs.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Is It Approximate Computing or Malicious Computing?
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Privacy Threats and Protection in Machine Learning.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Hardware Security and Trust: A New Battlefield of Information.
Proceedings of the Decision and Game Theory for Security - 11th International Conference, 2020

A Machine Learning based Approximate Computing Approach on Data Flow Graphs: Work-in-Progress.
Proceedings of the 20th International Conference on Embedded Software, 2020

TCIM: Triangle Counting Acceleration With Processing-In-MRAM Architecture.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Mitigating Adversarial Attacks for Deep Neural Networks by Input Deformation and Augmentation.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

MIDAS: Model Inversion Defenses Using an Approximate Memory System.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2020

BWOLF: Bit-Width Optimization for Statistical Divergence with -Logarithmic Functions.
Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020

2019
A Blockchain-Based Privacy-Preserving Authentication Scheme for VANETs.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Recent Attacks and Defenses on FPGA-based Systems.
ACM Trans. Reconfigurable Technol. Syst., 2019

A Survey on Recent Advances in Vehicular Network Security, Trust, and Privacy.
IEEE Trans. Intell. Transp. Syst., 2019

A Silicon PUF Based Entropy Pump.
IEEE Trans. Dependable Secur. Comput., 2019

Toward a Formal and Quantitative Evaluation Framework for Circuit Obfuscation Methods.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

HCIC: Hardware-Assisted Control-Flow Integrity Checking.
IEEE Internet Things J., 2019

Parallelizing SAT-based de-camouflaging attacks by circuit partitioning and conflict avoiding.
Integr., 2019

Pass and Run: A Privacy Preserving Delay Tolerant Network Communication Protocol for CyberVehicles.
IEEE Des. Test, 2019

Secure Routing Protocol based on Multi-objective Ant-colony-optimization for wireless sensor networks.
Appl. Soft Comput., 2019

A Secure and Low-overhead Active IC Metering Scheme.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

A Memristor-based Scan Hold Flip-Flop.
Proceedings of the 2019 IEEE Non-Volatile Memory Systems and Applications Symposium, 2019

LEAP: A Lightweight Encryption and Authentication Protocol for In-Vehicle Communications.
Proceedings of the 2019 IEEE Intelligent Transportation Systems Conference, 2019

Energy and Error Reduction using Variable Bit-width Optimization on Dynamic Fixed Point Format.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

PUF-PassSE: A PUF based Password Strength Enhancer for IoT Applications.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

Information Hiding behind Approximate Computation.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

LPN-based Device Authentication Using Resistive Memory.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

VoltJockey: Breaching TrustZone by Software-Controlled Voltage Manipulation over Multi-core Frequencies.
Proceedings of the 2019 ACM SIGSAC Conference on Computer and Communications Security, 2019

Research on the impact of different benchmark circuits on the representative path in FPGAs.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

A Polymorphic Circuit Interoperability Framework.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

VoltJockey: Breaking SGX by Software-Controlled Voltage-Induced Hardware Faults.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019

2018
Memristors for Secret Sharing-Based Lightweight Authentication.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Control Flow Integrity Based on Lightweight Encryption Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Spear and Shield: Evolution of Integrated Circuit Camouflaging.
J. Comput. Sci. Technol., 2018

HCIC: Hardware-assisted Control-flow Integrity Checking.
CoRR, 2018

A Privacy-Preserving Trust Model Based on Blockchain for VANETs.
IEEE Access, 2018

BARS: A Blockchain-Based Anonymous Reputation System for Trust Management in VANETs.
Proceedings of the 17th IEEE International Conference On Trust, 2018

Partial Scan Design Against Scan-Based Side Channel Attacks.
Proceedings of the 17th IEEE International Conference On Trust, 2018

An Entropy Analysis Based Intrusion Detection System for Controller Area Network in Vehicles.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

Balancing Testability and Security by Configurable Partial Scan Design.
Proceedings of the IEEE International Test Conference in Asia, 2018

Edge Computing based GPS Spoofing Detection Methods.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

A Machine Learning Attack Resistant Dual-mode PUF.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

A Novel Polymorphic Gate Based Circuit Fingerprinting Technique.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Securing the Systems of the Future - Techniques for a Shifting Attack Space.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

A reconfigurable scan network based IC identification for embedded devices.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

A New Scheme to Extract PUF Information by Scan Chain.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

A conflict-free approach for parallelizing SAT-based de-camouflaging attacks.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Polymorphic gate based IC watermarking techniques.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

A low-overhead PUF based on parallel scan design.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

A Delay based Plug-in-Monitor for Intrusion Detection in Controller Area Network.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018

Approximate Computing and Its Application to Hardware Security.
Proceedings of the Cyber-Physical Systems Security., 2018

2017
Group Cooperation With Optimal Resource Allocation in Wireless Powered Communication Networks.
IEEE Trans. Wirel. Commun., 2017

New Methods of Template Attack Based on Fault Sensitivity Analysis.
IEEE Trans. Multi Scale Comput. Syst., 2017

Why current secure scan designs fail and how to fix them?
Integr., 2017

Approximate Computing for Low Power and Security in the Internet of Things.
Computer, 2017

DoS attacks and countermeasures on network devices.
Proceedings of the 26th Wireless and Optical Communication Conference, 2017

Scan chain based IP fingerprint and identification.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

20 Years of research on intellectual property protection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A novel approximate computing based security primitive for the Internet of Things.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Practical IP watermarking and fingerprinting methods for ASIC designs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A Scalable and Resilient Microarchitecture Based on Multiport Binding for High-Radix Router Design.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017

Energy efficient runtime approximate computing on data flow graphs.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

An Empirical Study on Gate Camouflaging Methods Against Circuit Partition Attack.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

A Low-Cost GPS Spoofing Detector Design for Internet of Things (IoT) Applications.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

How to Secure Scan Design Against Scan-Based Side-Channel Attacks?
Proceedings of the 26th IEEE Asian Test Symposium, 2017

A New Active IC Metering Technique Based on Locking Scan Cells.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

A novel data format for approximate arithmetic computing.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

VOLtA: Voltage over-scaling based lightweight authentication for IoT applications.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

A practical cold boot attack on RSA private keys.
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017

2016
Rebuttal to "Comments on 'A PUF-FSM Binding Scheme for FPGA IP Protection and Pay-Per-Device Licensing"'.
IEEE Trans. Inf. Forensics Secur., 2016

A 3-D hand gesture signature based biometric authentication system for smartphones.
Secur. Commun. Networks, 2016

VLSI supply chain security risks and mitigation techniques: A survey.
Integr., 2016

Welcome.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Is the Secure IC camouflaging really secure?
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A new countermeasure against scan-based side-channel attacks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

An efficient framework for configurable RO PUF.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Security through obscurity: Integrated circuit obfuscation using don't care conditions.
Proceedings of the 2016 International Conference on Control, 2016

An ultra-low overhead LUT-based PUF for FPGA.
Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016

Secure and Low-Overhead Circuit Obfuscation Technique with Multiplexers.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Secret Sharing and Multi-user Authentication: From Visual Cryptography to RRAM Circuits.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Group Cooperation and Resource Allocation in Wireless Powered Communication Networks.
Proceedings of the 2016 IEEE Globecom Workshops, Washington, DC, USA, December 4-8, 2016, 2016

On the Mitigation of Interference Imposed by Intruders in Passive RFID Networks.
Proceedings of the Decision and Game Theory for Security - 7th International Conference, 2016

Physical unclonable functions-based linear encryption against code reuse attacks.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Digital Fingerprint: A Practical Hardware Security Primitive.
Proceedings of the Digital Fingerprinting, 2016

2015
Reconfigurable Binding against FPGA Replay Attacks.
ACM Trans. Design Autom. Electr. Syst., 2015

A PUF-FSM Binding Scheme for FPGA IP Protection and Pay-Per-Device Licensing.
IEEE Trans. Inf. Forensics Secur., 2015

Ultra-Low Overhead Dynamic Watermarking on Scan Design for Hard IP Protection.
IEEE Trans. Inf. Forensics Secur., 2015

A survey on memristor modeling and security applications.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

An improved scan design for minimization of test power under routing constraint.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A scan design method based on two complementary connection styles to minimize test power.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

DA Systemization of Knowledge: A Catalog of Prior Forward-Looking Initiatives.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

RRAM Based Lightweight User Authentication.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Template attack on masking AES based on fault sensitivity analysis.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

A practical circuit fingerprinting method utilizing observability don't care conditions.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Hardware Design and Verification Techniques for Supply Chain Risk Mitigation.
Proceedings of the 14th International Conference on Computer-Aided Design and Computer Graphics, 2015

Reliable and Anti-cloning PUFs Based on Configurable Ring Oscillators.
Proceedings of the 14th International Conference on Computer-Aided Design and Computer Graphics, 2015

Satisfiability Don't Care condition based circuit fingerprinting techniques.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Obtaining Statistically Random Information From Silicon Physical Unclonable Functions.
IEEE Trans. Emerg. Top. Comput., 2014

Designing Trusted Embedded Systems from Finite State Machines.
ACM Trans. Embed. Comput. Syst., 2014

A Survey on Silicon PUFs and Recent Advances in Ring Oscillator PUFs.
J. Comput. Sci. Technol., 2014

Trusted Integrated Circuits: The Problem and Challenges.
J. Comput. Sci. Technol., 2014

A DTN Routing Protocol for Vehicle Location Information Protection.
Proceedings of the 2014 IEEE Military Communications Conference, 2014

Enhancing Trust-Aware Routing by False Alarm Detection and Recovery.
Proceedings of the 2014 IEEE Military Communications Conference, 2014

A low-overhead dynamic watermarking scheme on scan design for easy authentication.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Design things for the internet of things: an EDA perspective.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

A survey on security and trust of FPGA-based systems.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

A Highly Flexible Ring Oscillator PUF.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Detection and Prevention of Selective Forwarding-Based Denial-of-Service Attacks in WSNs.
Int. J. Distributed Sens. Networks, 2013

Pass and run: A privacy preserving delay tolerant network communication protocol for CyberVehicles.
Proceedings of the International Conference on Connected Vehicles and Expo, 2013

FADER: False alarm detection and recovery for trust-aware routing in wireless sensor networks.
Proceedings of the International Conference on Connected Vehicles and Expo, 2013

FPGA IP protection by binding Finite State Machine to Physical Unclonable Function.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Design and implementation of a group-based RO PUF.
Proceedings of the Design, Automation and Test in Europe, 2013

Improving PUF security with regression-based distiller.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Design and Implementation of a Delay-Based PUF for FPGA IP Protection.
Proceedings of the 2013 International Conference on Computer-Aided Design and Computer Graphics, 2013

Incorporating temperature-leakage interdependency into dynamic voltage scaling for real-time systems.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012
Insider Threats against Trust Mechanism with Watchdog and Defending Approaches in Wireless Sensor Networks.
Proceedings of the 2012 IEEE Symposium on Security and Privacy Workshops, 2012

Scheduling for Multi-core Processor under Process and Temperature Variation.
Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012

2011
TALk: A Temperature-Aware Leakage Minimization Technique for Real-Time Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Improving dual Vt technology by simultaneous gate sizing and mechanical stress optimization.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

An energy efficient adaptive event detection scheme for wireless sensor network.
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

2010
Field Division Routing.
EURASIP J. Wirel. Commun. Netw., 2010

Enhancing dual-Vt design with consideration of on-chip temperature variation.
Proceedings of the 28th International Conference on Computer Design, 2010

Peak current reduction by simultaneous state replication and re-encoding.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

LISA: Maximizing RO PUF's Secret Extraction.
Proceedings of the HOST 2010, 2010

Behavioral level dual-vth design for reduced leakage power with thermal awareness.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Mesh-of-Trees and Alternative Interconnection Networks for Single-Chip Parallelism.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Peak Temperature Reduction by Physical Information Driven Behavioral Synthesis with Resource Usage Allocation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Leakage optimization using transistor-level dual threshold voltage cell library.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Temperature-Aware Cooperative Ring Oscillator PUF.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2009

Information hiding for trusted system design.
Proceedings of the 46th Design Automation Conference, 2009

Fingerprint - Iris Fusion Based Identification System Using a Single Hamming Distance Matcher.
Proceedings of the 2009 Symposium on Bio-inspired Learning and Intelligent Systems for Security, 2009

An Adaptive Energy Efficient Transmission Protocol in Wireless Ad-hoc Network.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009

2008
An FSM Reengineering Approach to Sequential Circuit Synthesis by State Splitting.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Energy efficient implementation of G.729 for wireless VoIP application.
Proceedings of the 2008 International Conference on Advanced Infocomm Technology, 2008

Minimizing point-to-point transmission energy with error correction coding and transmission power control.
Proceedings of the 2008 International Conference on Advanced Infocomm Technology, 2008

A Hardware-Assisted Data Hiding Based Approach in Building High-Performance Trusted Computing Systems.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008

An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing.
Proceedings of the 45th Design Automation Conference, 2008

A Power Efficient Path Key Establishment Algorithm for Wireless Sensor Networks.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008

2007
Probabilistic design of multimedia embedded systems.
ACM Trans. Embed. Comput. Syst., 2007

Low Power System Design by Combining Software Prefetching and Dynamic voltage Scaling.
J. Circuits Syst. Comput., 2007

Embedded Digital Signal Processing Systems.
EURASIP J. Embed. Syst., 2007

AffyProbeMiner: a web resource for computing or retrieving accurately redefined Affymetrix probe sets.
Bioinform., 2007

Power Management of Multicore Multiple Voltage Embedded Systems by Task Scheduling.
Proceedings of the 2007 International Conference on Parallel Processing Workshops (ICPP Workshops 2007), 2007

Simultaneous input vector selection and dual threshold voltage assignment for static leakage minimization.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Layout-Accurate Design and Implementation of a High-Throughput Interconnection Network for Single-Chip Parallel Processing.
Proceedings of the 15th Annual IEEE Symposium on High-Performance Interconnects, 2007

SecureGo: A Hardware-Software Co-Protection against Identity Theft in Online Transaction.
Proceedings of the 2007 ECSIS Symposium on Bio-inspired, 2007

ALT-DVS: Dynamic Voltage Scaling with Awareness of Leakage and Temperature for Real-Time Systems.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

Improving Key Distribution forWireless Sensor Networks.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

2006
A combined gate replacement and input vector control approach for leakage current reduction.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Energy-efficient embedded software implementation on multiprocessor system-on-chip with multiple voltages.
ACM Trans. Embed. Comput. Syst., 2006

Energy-driven detection scheme with guaranteed accuracy.
Proceedings of the Fifth International Conference on Information Processing in Sensor Networks, 2006

Temperature-aware leakage minimization technique for real-time systems.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Dual-Processor Design of Energy Efficient Fault-Tolerant System.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

A Mesh-of-Trees Interconnection Network for Single-Chip Parallel Processing.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

VLSI Design IP Protection: Solutions, New Challenges, and Opportunities.
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006

2005
Voltage Setup Problem for Embedded Systems With Multiple Voltages.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Analysis of energy reduction on dynamic voltage scaling-enabled systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

DSP Address Optimization Using Evolutionary Algorithms.
Proceedings of the 9th International Workshop on Software and Compilers for Embedded Systems, Dallas, Texas, USA, September 29, 2005

VLSI CAD tool protection by birthmarking design solutions.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Enhanced leakage reduction Technique by gate replacement.
Proceedings of the 42nd Design Automation Conference, 2005

FSM re-engineering and its application in low power state encoding.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Power minimization techniques on distributed real-time systems by global and local slack management.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

CASPER: An Integrated Energy-Driven Approach for Task Graph Scheduling on Distributed Embedded Systems.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
Power minimization in QoS sensitive systems.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Optimization-intensive watermarking techniques for decision problems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Effective iterative techniques for fingerprinting design IP.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Book review: Intellectual property protection in VLSI designs: Theory and practice, Hardcover, pp 183, plus XIX, Kluwer Academic Publishers, Boston, 2003, ISBN 1-4020-7320-8.
Microelectron. Reliab., 2004

How many solutions does a SAT instance have?
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

QoS-driven scheduling for multimedia applications.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Arbitrate-and-move primitives for high throughput on-chip interconnection networks.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Transferring performance gain from software prefetching to energy reduction.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Information Hiding in Finite State Machine.
Proceedings of the Information Hiding, 6th International Workshop, 2004

Soft IP Protection: Watermarking HDL Codes.
Proceedings of the Information Hiding, 6th International Workshop, 2004

Energy-efficient dual-voltage soft real-time system with (m, k)-firm deadline guarantee.
Proceedings of the 2004 International Conference on Compilers, 2004

Finding Redundant Constraints for FSM Minimization.
Proceedings of the Nineteenth National Conference on Artificial Intelligence, 2004

Generating 'Random' 3-SAT Instances with Specific Solution Space Structure.
Proceedings of the Nineteenth National Conference on Artificial Intelligence, 2004

Energy-Efficient Design of Distributed Sensor Networks.
Proceedings of the Handbook of Sensor Networks, 2004

2003
System synthesis of synchronous multimedia applications.
ACM Trans. Embed. Comput. Syst., 2003

QoP-driven scheduling for MPEG video decoding.
IEEE Trans. Consumer Electron., 2003

Minimal and maximal exposure path algorithms for wireless embedded sensor networks.
Proceedings of the 1st International Conference on Embedded Networked Sensor Systems, 2003

Exploring the Probabilistic Design Space of Multimedia Systems.
Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 2003

Introducing The Concept Of Design Reuse Into Undergraduate Digital Design Curriculum.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

A New Quality of Service Metric for Hard/Soft Real-Time Applications.
Proceedings of the 2003 International Symposium on Information Technology (ITCC 2003), 2003

Approaching the Maximum Energy Saving on Embedded Systems with Multiple Voltages.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Zero overhead watermarking technique for FPGA designs.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

On-line Voltage Scheduling for Multimedia Applications.
Proceedings of the First Workshop on Embedded Systems for Real-Time Multimedia, 2003

Energy-Efficient Multi-processor Implementation of Embedded Software.
Proceedings of the Embedded Software, Third International Conference, 2003

Energy reduction techniques for multimedia applications with tolerance to deadline misses.
Proceedings of the 40th Design Automation Conference, 2003

An on-line approach for power minimization in QoS sensitive systems.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Exposure in Wireless Sensor Networks: Theory and Practical Solutions.
Wirel. Networks, 2002

Techniques for energy-efficient communication pipeline design.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Publicly detectable watermarking for intellectual property authentication in VLSI design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Code Coverage-Based Power Estimation Techniques for Microprocessors.
J. Circuits Syst. Comput., 2002

Design Space Exploration for Energy-Efficient Secure Sensor Network.
Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002

2001
Exposure in wireless Ad-Hoc sensor networks.
Proceedings of the MOBICOM 2001, 2001

Keyless Public Watermarking for Intellectual Property Authentication.
Proceedings of the Information Hiding, 4th International Workshop, 2001

Intellectual Property Metering.
Proceedings of the Information Hiding, 4th International Workshop, 2001

What is the Limit of Energy Saving by Dynamic Voltage Scaling?
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Publicly Detectable Techniques for the Protection of Virtual Components.
Proceedings of the 38th Design Automation Conference, 2001

Hardware Metering.
Proceedings of the 38th Design Automation Conference, 2001

2000
Achieving utility arbitrarily close to the optimal with limited energy.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Energy minimization with guaranteed quality of service.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Fingerprinting intellectual property using constraint-addition.
Proceedings of the 37th Conference on Design Automation, 2000

Function-level power estimation methodology for microprocessors.
Proceedings of the 37th Conference on Design Automation, 2000

Fair watermarking techniques.
Proceedings of ASP-DAC 2000, 2000

1999
Power optimization of variable-voltage core-based systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

System Synthesis of Synchronous Multimedia Applications.
Proceedings of the 12th International Symposium on System Synthesis, 1999

Energy minimization of system pipelines using multiple voltages.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Hiding Signatures in Graph Coloring Solutions.
Proceedings of the Information Hiding, Third International Workshop, 1999

Power minimization using system-level partitioning of applications with quality of service requirements.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

The associative-skew clock routing problem.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

1998
Synthesis Techniques for Low-Power Hard Real-Time Systems on Variable Voltage Processors.
Proceedings of the 19th IEEE Real-Time Systems Symposium, 1998

Techniques for energy minimization of communication pipelines.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Analysis of watermarking techniques for graph coloring problem.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998


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