Jiseong Im

According to our database, Jiseong Im authored at least 4 papers between 2021 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Si-Based Dual-Gate Field-Effect Transistor Array for Low-Power On-Chip Trainable Hardware Neural Networks.

Kyu-Ho Lee, Dongseok Kwon, In-Seok Lee, Joon Hwang, Jiseong Im, Jong-Ho Bae, Woo Young Choi, Sung Yun Woo, Jong-Ho Lee

Adv. Intell. Syst., January, 2024

2022

On-Chip Trainable Spiking Neural Networks Using Time-To-First-Spike Encoding.

Jiseong Im, Jaehyeon Kim, Honam Yoo, Jong-Won Baek, Dongseok Kwon, Seongbin Oh, Jangsaeng Kim, Joon Hwang, Byung-Gook Park, Jong-Ho Lee

IEEE Access, 2022

2021

Direct Gradient Calculation: Simple and Variation-Tolerant On-Chip Training Method for Neural Networks.

Hyungyo Kim, Joon Hwang, Dongseok Kwon, Jangsaeng Kim, Min Kyu Park, Jiseong Im, Byung-Gook Park, Jong-Ho Lee

Adv. Intell. Syst., 2021

Spiking Neural Networks With Time-to-First-Spike Coding Using TFT-Type Synaptic Device Model.

Seongbin Oh, Soochang Lee, Sung Yun Woo, Dongseok Kwon, Jiseong Im, Joon Hwang, Jong-Ho Bae, Byung-Gook Park, Jong-Ho Lee

IEEE Access, 2021