Jiteshri Dasari

According to our database, Jiteshri Dasari authored at least 7 papers between 2022 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2026

Universal Formal Verification Approach for Modular Reduction Circuits.

Jiteshri Dasari, Maciej J. Ciesielski

Proceedings of the 39th International Conference on VLSI Design & 25th International Conference on Embedded Systems, 2026

2024

Verification and Debugging of Modular (2ⁿ - 1) Multipliers Using Linear Algebra Technique.

Jiteshri Dasari, Cunxi Yu, Maciej J. Ciesielski

Proceedings of the VLSI-SoC: Technology Advancement on SoC Design - 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024

Linear Algebra Approach to Verification of Modular $(2^{n}-1)$ Multipliers.

Jiteshri Dasari, Cunxi Yu, Maciej J. Ciesielski

Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024

Combining Formal Verification and Testing for Debugging of Arithmetic Circuits.

Jiteshri Dasari, Maciej J. Ciesielski

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

Efficient Formal Verification and Debugging of Arithmetic Divider Circuits.

Jiteshri Dasari, Maciej J. Ciesielski

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Formal Verification of Restoring Dividers made Fast and Simple.

Jiteshri Dasari, Maciej J. Ciesielski

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

Functional Verification of Arithmetic Circuits: Survey of Formal Methods.

Maciej J. Ciesielski, Atif Yasin, Jiteshri Dasari

Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022