Atif Yasin

According to our database, Atif Yasin authored at least 14 papers between 2016 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

Formal Verification of Divider Circuits by Hardware Reduction.

Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski

Proceedings of the 19th International Conference on Synthesis, 2023

2022

Functional Verification of Arithmetic Circuits: Survey of Formal Methods.

Maciej J. Ciesielski, Atif Yasin, Jiteshri Dasari

Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022

2020

Understanding Algebraic Rewriting for Arithmetic Circuit Verification: A Bit-Flow Model.

Maciej J. Ciesielski, Tiankai Su, Atif Yasin, Cunxi Yu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Formal Verification of Constrained Arithmetic Circuits using Computer Algebraic Approach.

Tiankai Su, Atif Yasin, Sébastien Pillement, Maciej J. Ciesielski

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Dual Approach to Solving SAT in Hardware.

Dinesh D. Narasimharaju, R. S. Suraj Rao, Akshaya Sandeep Waingade, Atif Yasin, Maciej J. Ciesielski

Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020

SPEAR: Hardware-based Implicit Rewriting for Square-root Circuit Verification.

Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Improving software requirements reasoning by novices: a story-based approach.

Rubia Fatima, Affan Yasin, Lin Liu, Jianmin Wang, Wasif Afzal, Atif Yasin

IET Softw., 2019

Functional Verification of Hardware Dividers using Algebraic Model.

Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Formal Verification of Integer Dividers: Division by a Constant.

Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Spectral approach to verifying non-linear arithmetic circuits.

Cunxi Yu, Tiankai Su, Atif Yasin, Maciej J. Ciesielski

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

Rewriting Environment for Arithmetic Circuit Verification.

Cunxi Yu, Atif Yasin, Tiankai Su, Alan Mishchenko, Maciej J. Ciesielski

Proceedings of the LPAR-22. 22nd International Conference on Logic for Programming, 2018

Computer Algebraic Approach to Verification and Debugging of Galois Field Multipliers.

Tiankai Su, Atif Yasin, Cunxi Yu, Maciej J. Ciesielski

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

Formal Verification of Truncated Multipliers Using Algebraic Approach and Re-Synthesis.

Tiankai Su, Cunxi Yu, Atif Yasin, Maciej J. Ciesielski

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

2016

Synergistic timing speculation for multi-threaded programs.

Atif Yasin, Jeff Jun Zhang, Hu Chen, Siddharth Garg, Sanghamitra Roy, Koushik Chakraborty

Proceedings of the 53rd Annual Design Automation Conference, 2016