Joe G. Xi

According to our database1, Joe G. Xi authored at least 4 papers between 1993 and 1996.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

1996
Jitter-tolerant clock routing in two-phase synchronous systems.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Useful-Skew Clock Routing With Gate Sizing for Low Power Design.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Buffer Insertion and Sizing Under Process Variations for Low Power Clock Distribution.
Proceedings of the 32st Conference on Design Automation, 1995

1993
Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993


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