Joe G. Xi

According to our database, Joe G. Xi authored at least 4 papers between 1993 and 1997.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1997

Useful-Skew Clock Routing with Gate Sizing for Low Power Design.

Joe G. Xi, Wayne Wei-Ming Dai

J. VLSI Signal Process., 1997

1996

Jitter-tolerant clock routing in two-phase synchronous systems.

Joe G. Xi, Wayne Wei-Ming Dai

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1995

Buffer Insertion and Sizing Under Process Variations for Low Power Clock Distribution.

Joe G. Xi, Wayne Wei-Ming Dai

Proceedings of the 32st Conference on Design Automation, 1995

1993

Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models.

Qing Zhu, Wayne Wei-Ming Dai, Joe G. Xi

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993