Wayne Wei-Ming Dai

Affiliations:
  • University of California, Santa Cruz, USA


According to our database1, Wayne Wei-Ming Dai authored at least 62 papers between 1985 and 2006.

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Bibliography

2006
Yield-preferred via insertion based on novel geotopological technology.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Design and Analysis of Area-IO DRAM/Logic Integration with System-in-a-Package(SiP).
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Area-IO DRAM/logic integration with system-in-a-package (SiP).
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Area minimization of power distribution network using efficient nonlinear programming techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

A Domain-Specific Cell Based ASIC Design Methodology for Digital Signal Processing Applications.
Proceedings of the 2004 Design, 2004

SPICE compatible circuit models for partial reluctance K.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
TEG: a new post-layout optimization method.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Electrical and Thermal Analysis for System-in-a-Package (SiP) Implementation Platform.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

2002
Crosstalk noise estimation for noise management.
Proceedings of the 39th Design Automation Conference, 2002

2001
Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Fast 3-D Inductance Extraction in Lossy Multi-Layer Substrate.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Beyond the red brick wall (panel): challenges and solutions in 50nm physical design.
Proceedings of ASP-DAC 2001, 2001

KSim: a stable and efficient RKC simulator for capturing on-chip inductance effect.
Proceedings of ASP-DAC 2001, 2001

2000
How to Efficiently Capture On-Chip Inductance Effects: Introducing a New Circuit Element K.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Design of C++ Class Library and Bit-Serial Compiler for Variable-Precision Datapath Synthesis on Adaptive Computing Systems.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

Integration of large-scale FPGA and DRAM in a package using chip-on-chip technology.
Proceedings of ASP-DAC 2000, 2000

Modeling and analysis of integrated spiral inductors for RF system-in-package.
Proceedings of ASP-DAC 2000, 2000

1999
An efficient sequential quadratic programming formulation of optimal wire spacing for cross-talk noise avoidance routing.
Proceedings of the 1999 International Symposium on Physical Design, 1999

1998
Topology constrained rectilinear block packing for layout reuse.
Proceedings of the 1998 International Symposium on Physical Design, 1998

Arbitrary rectilinear block packing based on sequence pair.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Efficient Three-Dimensional Extraction Based on Static and Full-Wave Layered Green's Functions.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Useful-Skew Clock Routing with Gate Sizing for Low Power Design.
J. VLSI Signal Process., 1997

Post-route optimization for improved yield using a rubber-band wiring model.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Delay bounded buffered tree construction for timing driven floorplanning.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Critical technologies and methodologies for systems-on-chips (tutorial).
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Chip Parasitic Extraction and Signal Integrity Verification (Extended Abstract).
Proceedings of the 34st Conference on Design Automation, 1997

General floorplanning with L-shaped, T-shaped and soft blocks based on bounded slicing grid structure.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

Bit-serial pipeline synthesis and layout for large-scale configurable systems.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996
Planar clock routing for high performance chip and package co-design.
IEEE Trans. Very Large Scale Integr. Syst., 1996

High-speed clock network sizing optimization based on distributed RC and lossy RLC interconnect models.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Interchangeable pin routing with application to package layout.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Jitter-tolerant clock routing in two-phase synchronous systems.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

A novel dimension reduction technique for the capacitance extraction of 3D VLSI interconnects.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

A Method for Generating Random Circuits and Its Application to Routability Measurement.
Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, 1996

Bit-serial pipeline synthesis for multi-FPGA systems with C++ design capture.
Proceedings of the 4th IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '96), 1996

Fast Parameters Extraction of General Three-Dimension Interconnects Using Geometry Independent Measured Equation of Invariance.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Transformation of min-max optimization to least-square estimation and application to interconnect design optimization.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Transient analysis of coupled transmission lines characterized with the frequency-dependent losses using scattering-parameter based macromodel.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Single-layer fanout routing and routability analysis for Ball Grid Arrays.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Design of FPGAs with Area I/O for Field Programmable MCM.
Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995

High-Level Bit-Serial Datapath Synthesis for Multi-FPGA Systems.
Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995

Buffer Insertion and Sizing Under Process Variations for Low Power Clock Distribution.
Proceedings of the 32st Conference on Design Automation, 1995

Pin assignment and routing on a single-layer Pin Grid Array.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994
Optimal Design of Self-Damped Lossy Transmission Lines for Multichip Modules.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Capturing time-of-flight delay for transient analysis based on scattering parameter macromodel.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Hight-Performance Datapath Implementation on Field-Programmable Multi-Chip Module (FPMCM).
Proceedings of the Field-Programmable Logic, 1994

1993
SURF: Rubber-Band Routing System for Multichip Modules.
IEEE Des. Test Comput., 1993

Guest Editor's Introduction.
IEEE Des. Test Comput., 1993

S-parameter based macro model of distributed-lumped networks using Pade approximation.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Optimal single hop multiple bus networks.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

S-Parameter Based Macro Model of Distributed-Lumped Networks Using Exponentially Decayed Polynomial Function.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
Perfect-balance planar clock routing with minimal path-length.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

1991
Routability of a Rubber-Band Sketch.
Proceedings of the 28th Design Automation Conference, 1991

Topological Routing in SURF: Generating a Rubber-Band sketch.
Proceedings of the 28th Design Automation Conference, 1991

1990
Rubber Band Routing and Dynamic Data Representation.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

1989
Hierarchical placement and floorplanning in BEAR.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

1988
Hierarchical placement for macrocells: a 'meet in the middle' approach.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

1987
Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

A Dynamic and Efficient Representation of Building-Block Layout.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1985
Routing Region Definition and Ordering Scheme for Building-Block Layout.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985


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