John Richard E. Hizon

According to our database1, John Richard E. Hizon authored at least 23 papers between 2012 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Design and Implementation of a Pipelined RV32IMC Processor with Interrupt Support for Large-Scale Wireless Sensor Networks.
Proceedings of the 2020 IEEE Region 10 Conference, 2020


Designing a Class E Power Amplifier through Modeling in Verilog-A.
Proceedings of the International SoC Design Conference, 2020

5 Gb/s Optical Transceiver for MEMS Tunable HCG-VCSEL in 65 nm CMOS.
Proceedings of the International SoC Design Conference, 2020

An Interface for Shock Inputs in Piezoelectric Energy Harvesting using Synchronous Electric Charge Extraction.
Proceedings of the International SoC Design Conference, 2020

Design Space Exploration of a 512KB STT-Assisted SOT MRAM Cache.
Proceedings of the International SoC Design Conference, 2020

A Top-Down Approach for Low Noise Amplifier Design using Verilog-A.
Proceedings of the International SoC Design Conference, 2020

2019
A 0.5 V Low-Power All-Digital Phase-Locked Loop in 65 nm Complementary Metal-Oxide-Semiconductor Process.
J. Low Power Electron., 2019

Design and Implementation a Self-starting Thermal Energy Harvester with Resonant Startup and Maximum Power Point Tracking Capabilities/or Wireless Sensor Nodes.
Proceedings of the 2019 International SoC Design Conference, 2019

An SDR-based WSN Testbed for RF Front End Simulation and Experimentation.
Proceedings of the 2019 International SoC Design Conference, 2019

2018
A gm/ID Based Algorithm for the Design of CMOS Miller Operational Amplifiers in 65 nm Technology.
Proceedings of the TENCON 2018, 2018

A 0.5V Low-Power All-Digital Phase-Locked Loop in 65nm CMOS Process for Wireless Sensing Applications.
Proceedings of the TENCON 2018, 2018

Design of Multiple Prediction Complexity Configurations for an FPGA-Based H.264 Baseline Profile Encoder.
Proceedings of the TENCON 2018, 2018

Low Power Converter for Capacitive Sensors Using Capacitance-to-Pulse Width Modulation.
Proceedings of the TENCON 2018, 2018

A Study on Coarse Stage Bit Allocation to Improve Power Efficiency of a 10-bit Coarse-Fine SAR ADC Implemented in 65nm CMOS Process for Environmental Sensing Applications.
Proceedings of the TENCON 2018, 2018


2016
PVT-aware digital techniques for a power line energy-harvesting sensor node.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2014
A reconfigurable FGMOS based OTA-C filter.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Timing analysis and optimization of voltage scaled CMOS digital circuits with dual-Vth devices.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
Improving an undergraduate laboratory course for semiconductor device theory to enhance an IC design program.
Proceedings of the 2013 IEEE International Conference on Microelectronic Systems Education, 2013

Driving Philippine microelectronics education development with multi-university collaboration.
Proceedings of the 2013 IEEE International Conference on Microelectronic Systems Education, 2013

2012
A high transconductance efficiency FGMOS OTA for gm-C ladder filters.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

A compact linearly tunable low voltage triode OTA using self-cascodes.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012


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