Anastacia B. Alvarez
Orcid: 0000-0002-9988-367X
According to our database1,
Anastacia B. Alvarez
authored at least 35 papers
between 2010 and 2024.
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Bibliography
2024
Proceedings of the 8th International Conference on Machine Learning and Soft Computing, 2024
2023
Integration of In-Memory Computing Capabilities to a Self-Matching Complementary-Reference Sensing Scheme for TST-MRAM.
Proceedings of the 20th International SoC Design Conference, 2023
Proceedings of the 20th International SoC Design Conference, 2023
2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
Proceedings of the 18th International SoC Design Conference, 2021
2020
Energy-Quality Scalable Memory-Frugal Feature Extraction for Always-On Deep Sub-mW Distributed Vision.
IEEE Access, 2020
Power and Area Oriented Implementations of Lightweight Cryptographic Algorithms for Wireless Sensor Networks.
Proceedings of the 2020 IEEE Region 10 Conference, 2020
Design and Implementation of a Pipelined RV32IMC Processor with Interrupt Support for Large-Scale Wireless Sensor Networks.
Proceedings of the 2020 IEEE Region 10 Conference, 2020
Bit-Selection Control for Energy-Efficient Handwritten Digits Recognition Hyperdimensional Computing Architecture.
Proceedings of the 2020 IEEE Region 10 Conference, 2020
Proceedings of the 2020 IEEE Region 10 Conference, 2020
Proceedings of the International SoC Design Conference, 2020
Proceedings of the International SoC Design Conference, 2020
An Interface for Shock Inputs in Piezoelectric Energy Harvesting using Synchronous Electric Charge Extraction.
Proceedings of the International SoC Design Conference, 2020
Proceedings of the International SoC Design Conference, 2020
Proceedings of the 32nd International Conference on Microelectronics, 2020
2019
A 0.5 V Low-Power All-Digital Phase-Locked Loop in 65 nm Complementary Metal-Oxide-Semiconductor Process.
J. Low Power Electron., 2019
Design and Implementation a Self-starting Thermal Energy Harvester with Resonant Startup and Maximum Power Point Tracking Capabilities/or Wireless Sensor Nodes.
Proceedings of the 2019 International SoC Design Conference, 2019
2018
Fully Synthesizable PUF Featuring Hysteresis and Temperature Compensation for 3.2% Native BER and 1.02 fJ/b in 40 nm.
IEEE J. Solid State Circuits, 2018
A gm/ID Based Algorithm for the Design of CMOS Miller Operational Amplifiers in 65 nm Technology.
Proceedings of the TENCON 2018, 2018
Hardware-Based Model of Node Clustering Using Q-Learning for Wireless Sensor Networks.
Proceedings of the TENCON 2018, 2018
A 0.5V Low-Power All-Digital Phase-Locked Loop in 65nm CMOS Process for Wireless Sensing Applications.
Proceedings of the TENCON 2018, 2018
An Ultra-Low Power Direct Active-RF Detection Wake-Up Receiver with Noise-Cancelling Envelope Detector in 65 nm CMOS Process.
Proceedings of the TENCON 2018, 2018
A 2.4 GHz Energy-efficient Short-range Receiver with Wake-up and Multiple Gain Settings for Wireless Sensor Networks.
Proceedings of the TENCON 2018, 2018
Design and Implementation of a Thermoelectric Energy Harvesting Interface Circuit with Maximum Power Point Tracking and Self-Startup Capability for Wireless Sensor Nodes.
Proceedings of the TENCON 2018, 2018
A Study on Coarse Stage Bit Allocation to Improve Power Efficiency of a 10-bit Coarse-Fine SAR ADC Implemented in 65nm CMOS Process for Environmental Sensing Applications.
Proceedings of the TENCON 2018, 2018
Proceedings of the 2018 New Generation of CAS, 2018
2017
A fully-synthesizable C-element based PUF featuring temperature variation compensation with native 2.8% BER, 1.02fJ/b at 0.8-1.0V in 40nm.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
EQSCALE: Energy-quality scalable feature extraction engine for Sub-mW real-time video processing with 0.55 mm<sup>2</sup> area in 40nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
Static Physically Unclonable Functions for Secure Chip Identification With 1.9-5.8% Native Bit Instability at 0.6-1 V and 15 fJ/bit in 65 nm.
IEEE J. Solid State Circuits, 2016
2015
A 65-nm 25.1-ns 30.7-fJ Robust Subthreshold Level Shifter With Wide Conversion Range.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
14.3 15fJ/b static physically unclonable functions for secure chip identification with <2% native bit instability and 140× Inter/Intra PUF hamming distance separation in 65nm.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2013
Robustness-driven energy-efficient ultra-low voltage standard cell design with intra-cell mixed-Vt methodology.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
2011
Proceedings of the 13th UKSim-AMSS International Conference on Computer Modelling and Simulation, Cambridge University, Emmanuel College, Cambridge, UK, 30 March, 2011
2010
A Simulation of Cache Sub-banking and Block Buffering as Power Reduction Techniques for Multiprocessor Cache Design.
Proceedings of the 12th UKSim, 2010
Simulation of Standard Benchmarks in Hardware Implementations of L2 Cache Models in Verilog HDL.
Proceedings of the 12th UKSim, 2010