Louis P. Alarcón

According to our database1, Louis P. Alarcón authored at least 13 papers between 2006 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Passive 5.8GHz RF Energy Harvester in 65nm CMOS.
Proceedings of the IEEE Region 10 Conference, 2023

2017
A 450kHz PVT-resilient all-digital BPSK demodulator for energy harvesting sensor nodes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Smart-wire: A 0.5V 44uW 0°C to 100°C power-line energy harvesting sensor node.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
PVT-aware digital techniques for a power line energy-harvesting sensor node.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2014
Timing analysis and optimization of voltage scaled CMOS digital circuits with dual-Vth devices.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
Improving an undergraduate laboratory course for semiconductor device theory to enhance an IC design program.
Proceedings of the 2013 IEEE International Conference on Microelectronic Systems Education, 2013

Driving Philippine microelectronics education development with multi-university collaboration.
Proceedings of the 2013 IEEE International Conference on Microelectronic Systems Education, 2013

2012
Active RFID: Perpetual wireless communications platform for sensors.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2011
A low-leakage parallel CRC generator for ultra-low power applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
Ultralow-Power Design in Near-Threshold Region.
Proc. IEEE, 2010

2009
Asynchronous Computing in Sense Amplifier-Based Pass Transistor Logic.
IEEE Trans. Very Large Scale Integr. Syst., 2009

2007
Exploring Very Low-Energy Logic: A Case Study.
J. Low Power Electron., 2007

2006
A study of floating-point architectures for pipelined RISC processors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006


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