John Y. Oliver

Orcid: 0000-0003-2877-6751

According to our database1, John Y. Oliver authored at least 17 papers between 2003 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

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Bibliography

2022
Co-curricular Engagement of Transfer Students.
Proceedings of the IEEE Frontiers in Education Conference, 2022

2014
Twill: A Hybrid Microcontroller-FPGA Framework for Parallelizing Single-Threaded C Programs.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

2013
A semi-autonomous embedded systems course.
Proceedings of the IEEE Frontiers in Education Conference, 2013

2012
A Study of Reusing Smartphones to Augment Elementary School Education.
Int. J. Handheld Comput. Res., 2012

Work in progress: Outreach assessment: Measuring engagement: An integrated approach for learning.
Proceedings of the IEEE Frontiers in Education Conference, 2012

2010
Smartphone Evolution and Reuse: Establishing a More Sustainable Model.
Proceedings of the 39th International Conference on Parallel Processing, 2010

A case for smartphone reuse to augment elementary school education.
Proceedings of the International Green Computing Conference 2010, 2010

2008
Credit-based dynamic reliability management using online wearout detection.
Proceedings of the 5th Conference on Computing Frontiers, 2008

2007
Using Application Bisection Bandwidth to Guide Tile Size Selection for the Synchroscalar Tile-Based Architecture.
Trans. High Perform. Embed. Archit. Compil., 2007

Life Cycle Aware Computing: Reusing Silicon Technology.
Computer, 2007

2006
Synchroscalar: Evaluation of an embedded, multi-core architecture for media applications.
J. Embed. Comput., 2006

Characterization of Error-Tolerant Applications when Protecting Control Data.
Proceedings of the 2006 IEEE International Symposium on Workload Characterization, 2006

Tile size selection for low-power tile-based architectures.
Proceedings of the Third Conference on Computing Frontiers, 2006

2004
Efficient orchestration of sub-word parallelism in media processors.
Proceedings of the SPAA 2004: Proceedings of the Sixteenth Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2004

Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor.
Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004

2003
Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture.
Proceedings of the Power-Aware Computer Systems, Third International Workshop, 2003

Improving DSP Performance with a Small Amount of Field Programmable Logic.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003


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