Ravishankar Rao

According to our database1, Ravishankar Rao authored at least 22 papers between 2002 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2009
Fast and Accurate Prediction of the Steady-State Throughput of Multicore Processors Under Thermal Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Throughput optimal task allocation under thermal constraints for multi-core processors.
Proceedings of the 46th Design Automation Conference, 2009

2008
Analytical results for design space exploration of multi-core processors employing thread migration.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Efficient online computation of core speeds to maximize the throughput of thermally constrained multi-core processors.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

2007
Energy optimal speed control of a producer-consumer device pair.
ACM Trans. Embed. Comput. Syst., 2007

Throughput of multi-core processors under thermal constraints.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Performance optimal processor throttling under thermal constraints.
Proceedings of the 2007 International Conference on Compilers, 2007

2006
Energy-Optimal Speed Control of a Generic Device.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Synchroscalar: Evaluation of an embedded, multi-core architecture for media applications.
J. Embed. Comput., 2006

An optimal analytical solution for processor speed control with thermal constraints.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Segmented Bitline Cache: Exploiting Non-uniform Memory Access Patterns.
Proceedings of the High Performance Computing, 2006

Tile size selection for low-power tile-based architectures.
Proceedings of the Third Conference on Computing Frontiers, 2006

2005
Battery optimization vs energy optimization: which to choose and when?
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Energy optimal speed control of devices with discrete speed sets.
Proceedings of the 42nd Design Automation Conference, 2005

An efficient combinationality check technique for the synthesis of cyclic combinational circuits.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor.
Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004

Energy optimization for a two-device data flow chain.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Disk drive energy optimization for audio-video applications.
Proceedings of the 2004 International Conference on Compilers, 2004

2003
Battery Modeling for Energy-Aware System Design.
Computer, 2003

Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture.
Proceedings of the Power-Aware Computer Systems, Third International Workshop, 2003

Analysis of discharge techniques for multiple battery systems.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

2002
HLSpower: Hybrid Statistical Modeling of the Superscalar Power-Performance Design Space.
Proceedings of the High Performance Computing, 2002


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