According to our database1, Jonas Skeppstedt
Legend:Book In proceedings Article PhD thesis Other
Finding fast action selectors for dataflow actors.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014
Compiler Controlled Prefetching for Multiprocessors Using Low-Overhead Traps and Prefetch Engines.
J. Parallel Distrib. Comput., 2000
Evaluation of Compiler-Controlled Updating to Reduce Coherence-Miss Penalties in Shared-Memory Multiprocessors.
J. Parallel Distrib. Comput., 1999
An evaluation of hardware-based and compiler-controlled optimizations of snooping cache protocols.
Future Generation Comp. Syst., 1998
Hybrid compiler/hardware prefetching for multiprocessors using low-overhead cache miss traps.
Proceedings of the 1997 International Conference on Parallel Processing (ICPP '97), 1997
A Performance Tuning Approach for Shared-Memory Multiprocessors.
Proceedings of the Euro-Par '97 Parallel Processing, 1997
Overcoming Limitations of Prefetching in Multiprocessors by Compiler-Initiated Coherence Actions.
Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), 1997
Using Dataflow Analysis Techniques to Reduce Ownership Overhead in Cache Coherence Protocols.
ACM Trans. Program. Lang. Syst., 1996
The design of a non-blocking load processor architecture.
Microprocessors and Microsystems - Embedded Hardware Design, 1996
Essential Misses and Data Traffic in Coherence Protocols.
J. Parallel Distrib. Comput., 1995
A compiler algorithm that reduces read latency in ownership-based cache coherence protocols.
Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, 1995
Simple Compiler Algorithms to Reduce Ownership Operhead in Cache Coherence Protocols.
Proceedings of the ASPLOS-VI Proceedings, 1994
The Detection and Elimination of Useless Misses in Multiprocessors.
Proceedings of the 20th Annual International Symposium on Computer Architecture, 1993