Jörn W. Janneck
According to our database1,
Jörn W. Janneck
authored at least 70 papers
between 1998 and 2022.
Collaborative distances:
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Bibliography
2022
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2022
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2022
2021
CoRR, 2021
Generating hardware and software for RISC-V cores generated with Rocket Chip generator.
Proceedings of the 34th IEEE International System-on-Chip Conference, 2021
Triggered Scheduling: Efficient Detection of Dataflow Network Idleness on Heterogeneous Systems.
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021
2020
ACM Trans. Embed. Comput. Syst., 2020
2019
Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019
2017
Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Proceedings of the 8th International Conference on Ambient Systems, 2017
2016
Dataflow Programs Analysis and Optimization Using Model Predictive Control Techniques - Two Examples of Bounded Buffer Scheduling: Deadlock Avoidance and Deadlock Recovery Strategies.
J. Signal Process. Syst., 2016
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016
Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016
2015
Implementing a streaming application on a processor array: A case study on the Epiphany architecture.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015
2014
Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014
Proceedings of the 17th International Workshop on Software and Compilers for Embedded Systems, 2014
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014
TURNUS: An open-source design space exploration framework for dynamic stream programs.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014
Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive control.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014
2013
Proceedings of the Handbook of Signal Processing Systems, 2013
Signal Process. Image Commun., 2013
Partitioning and optimization of high level stream applications for multi clock domain architectures.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Design space exploration of high level stream programs on parallel architectures: A focus on the buffer size minimization and optimization problem.
Proceedings of the 8th International Symposium on Image and Signal Processing and Analysis, 2013
Proceedings of the 8th International Symposium on Image and Signal Processing and Analysis, 2013
Design space exploration and implementation of RVC-CAL applications using the TURNUS framework.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013
Turnus: A unified dataflow design space exploration framework for heterogeneous parallel systems.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013
Proceedings of the Fifth International Conference on Computational Intelligence, 2013
Proceedings of the 2013 Asilomar Conference on Signals, 2013
Proceedings of the 2013 Asilomar Conference on Signals, 2013
Multi-clock domain optimization for reconfigurable architectures in high-level dataflow applications.
Proceedings of the 2013 Asilomar Conference on Signals, 2013
2012
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012
Dataflow programming in CAL - balancing expressiveness, analyzability, and implementability.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012
2011
J. Signal Process. Syst., 2011
Synthesizing Hardware from Dataflow Programs - An MPEG-4 Simple Profile Decoder Case Study.
J. Signal Process. Syst., 2011
J. Signal Process. Syst., 2011
J. Signal Process. Syst., 2011
Optimization of portable parallel signal processing applications by design space exploration of dataflow programs.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011
2010
Reconfigurable video coding: a stream programming approach to the specification of new video coding standards.
Proceedings of the First Annual ACM SIGMM Conference on Multimedia Systems, 2010
Automated generation of an efficient MPEG-4 Reconfigurable Video Coding decoder implementation.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010
Proceedings of the Handbook of Signal Processing Systems, 2010
2009
IEEE Trans. Circuits Syst. Video Technol., 2009
An Integrated Environment for HW/SW Co-design based on a CAL Specification and HW/SW Code Generators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
SIGARCH Comput. Archit. News, 2008
Automatic software synthesis of dataflow program: An MPEG-4 simple profile decoder case study.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008
Proceedings of the 2008 IEEE International Conference on Multimedia and Expo, 2008
2007
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
2005
Counting Interface Automata and their Application in Static Analysis of Actor Models.
Proceedings of the Third IEEE International Conference on Software Engineering and Formal Methods (SEFM 2005), 2005
2004
IEEE Trans. Control. Syst. Technol., 2004
Softw. Syst. Model., 2004
2003
Proceedings of the 2003 IEEE Symposium on Human Centric Computing Languages and Environments (HCC 2003), 2003
Proceedings of the Fundamental Approaches to Software Engineering, 2003
2002
Describing the Syntax and Semantics of UML Statecharts in a Heterogeneous Modelling Environment.
Proceedings of the Diagrammatic Representation and Inference, 2002
2001
Proceedings of the 2002 IEEE CS International Symposium on Human-Centric Computing Languages and Environments (HCC 2001), 2001
Proceedings of the 2002 IEEE CS International Symposium on Human-Centric Computing Languages and Environments (HCC 2001), 2001
1998
Proceedings of the 12th Workshop on Parallel and Distributed Simulation, 1998
Proceedings of the 4th International Conference on Engineering of Complex Computer Systems (ICECCS '98), 1998