Jongmin Lee

According to our database, Jongmin Lee authored at least 11 papers between 2009 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2017

A Way-Filtering-Based Dynamic Logical-Associative Cache Architecture for Low-Energy Consumption.

Jungwoo Park, Jongmin Lee, Soontae Kim

IEEE Trans. Very Large Scale Integr. Syst., 2017

TLB Index-Based Tagging for Reducing Data Cache and TLB Energy Consumption.

Jesung Kim, Jongmin Lee, Soontae Kim

IEEE Trans. Computers, 2017

2016

Write Buffer-Oriented Energy Reduction in the L1 Data Cache for Embedded Systems.

Jongmin Lee, Soontae Kim

IEEE Trans. Very Large Scale Integr. Syst., 2016

2015

Filter Data Cache: An Energy-Efficient Small L0 Data Cache Architecture Driven byMiss Cost Reduction.

Jongmin Lee, Soontae Kim

IEEE Trans. Computers, 2015

2014

Ternary cache: Three-valued MLC STT-RAM caches.

Seokin Hong, Jongmin Lee, Soontae Kim

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013

Skinflint DRAM system: Minimizing DRAM chip writes for low power.

Yebin Lee, Soontae Kim, Seokin Hong, Jongmin Lee

Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

2012

Adopting TLB index-based tagging to data caches for tag energy reduction.

Jongmin Lee, Soontae Kim

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

2011

Residue cache: a low-energy low-area L2 cache architecture via compression and partial hits.

Soontae Kim, Jongmin Lee, Jesung Kim, Seokin Hong

Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

TLB index-based tagging for cache energy reduction.

Jongmin Lee, Seokin Hong, Soontae Kim

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

2010

Write buffer-oriented energy reduction in the L1 data cache of two-level caches for the embedded system.

Soontae Kim, Jongmin Lee

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009

An energy-delay efficient 2-level data cache architecture for embedded system.

Jongmin Lee, Soontae Kim

Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009