Soontae Kim
Orcid: 0000-0001-5106-8409Affiliations:
- Korea Advanced Institute of Science and Technology, Daejeon, South Korea
- Information and Communications University, Daejeon, South Korea (former)
- University of South Florida, Tampa, FL, USA (2004 - 2007)
- Pennsylvania State University, University Park, PA, USA (PhD 2003)
According to our database1,
Soontae Kim
authored at least 84 papers
between 2001 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024
Zero and Narrow-Width Value-Aware Compression for Quantized Convolutional Neural Networks.
IEEE Trans. Computers, January, 2024
2023
PR-SSD: Maximizing Partial Read Potential by Exploiting Compression and Channel-Level Parallelism.
IEEE Trans. Computers, March, 2023
Effective Emoticon Suggestion Technique Based on Active Emotional Input Using Facial Expressions and Heart Rate Signals.
Sensors, 2023
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
Estimated State-Based Optimal Path Planning and Control System for Lane-Keeping of Semi-Trailer Trucks.
Proceedings of the 25th IEEE International Conference on Intelligent Transportation Systems, 2023
2022
Efficient Integrity-Tree Structure for Convolutional Neural Networks through Frequent Counter Overflow Prevention in Secure Memories.
Sensors, 2022
Exploiting Inter-block Entropy to Enhance the Compressibility of Blocks with Diverse Data.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
ENCORE Compression: Exploiting Narrow-width Values for Quantized Deep Neural Networks.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
Update Frequency-Directed Subpage Management for Mitigating Garbage Collection and DRAM Overheads.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
CID: Co-Architecting Instruction Cache and Decompression System for Embedded Systems.
IEEE Trans. Computers, 2021
ECC-United Cache: Maximizing Efficiency of Error Detection/Correction Codes in Associative Cache Memories.
IEEE Trans. Computers, 2021
2020
SALE: Smartly Allocating Low-Cost Many-Bit ECC for Mitigating Read and Write Errors in STT-RAM Caches.
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Proceedings of the ICS '20: 2020 International Conference on Supercomputing, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
Interpage-Based Endurance-Enhancing Lower State Encoding for MLC and TLC Flash Memory Storages.
IEEE Trans. Very Large Scale Integr. Syst., 2019
J. Supercomput., 2019
MH Cache: A Mult Stephen Jarvisi-retention STT-RAM-based Low-power Last-level Cache for Mobile Hardware Rendering Systems.
ACM Trans. Archit. Code Optim., 2019
2018
ACM Trans. Embed. Comput. Syst., 2018
IEEE Trans. Computers, 2018
Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, 2018
2017
A Way-Filtering-Based Dynamic Logical-Associative Cache Architecture for Low-Energy Consumption.
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Computers, 2017
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
Flexible ECC Management for Low-Cost Transient Error Protection of Last-Level Caches.
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Computers, 2016
Designing a Resilient L1 Cache Architecture to Process Variation-Induced Access-Time Failures.
IEEE Trans. Computers, 2016
Floating-ECC: Dynamic Repositioning of Error Correcting Code Bits for Extending the Lifetime of STT-RAM Caches.
IEEE Trans. Computers, 2016
MofySim: A mobile full-system simulation framework for energy consumption and performance analysis.
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
Low-Cost Control Flow Protection via Available Redundancies in the Microprocessor Pipeline.
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Computers, 2015
A Low-Cost Mechanism Exploiting Narrow-Width Values for Tolerating Hard Faults in ALU.
IEEE Trans. Computers, 2015
Filter Data Cache: An Energy-Efficient Small L0 Data Cache Architecture Driven byMiss Cost Reduction.
IEEE Trans. Computers, 2015
Proceedings of the IEEE 5th International Conference on Consumer Electronics - Berlin, 2015
2014
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
2013
Des. Autom. Embed. Syst., 2013
Performance-controllable shared cache architecture for multi-core soft real-time systems.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013
Macho: A failure model-oriented adaptive cache architecture to enable near-threshold voltage scaling.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Predictive routing for mobile sinks in wireless sensor networks: a milestone-based approach.
J. Supercomput., 2012
Pers. Ubiquitous Comput., 2012
J. Netw. Comput. Appl., 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
Low-cost control flow error protection by exploiting available redundancies in the pipeline.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
Enhanced buffer management policy that utilises message properties for delay-tolerant networks.
IET Commun., 2011
Residue cache: a low-energy low-area L2 cache architecture via compression and partial hits.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Dynamic scheduling algorithm and its schedulability analysis for certifiable dual-criticality systems.
Proceedings of the 11th International Conference on Embedded Software, 2011
Realizing near-true voltage scaling in variation-sensitive l1 caches via fault buffers.
Proceedings of the 14th International Conference on Compilers, 2011
Proceedings of the 2011 IEEE Asia-Pacific Services Computing Conference, 2011
2010
Proceedings of the MASCOTS 2010, 2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the 28th International Conference on Computer Design, 2010
Write buffer-oriented energy reduction in the L1 data cache of two-level caches for the embedded system.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
SimTag: Exploiting tag bits similarity to improve the reliability of the data caches.
Proceedings of the Design, Automation and Test in Europe, 2010
2009
A Framework for Correction of Multi-Bit Soft Errors in L2 Caches Based on Redundancy.
IEEE Trans. Very Large Scale Integr. Syst., 2009
IEEE Trans. Computers, 2009
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
2007
Microprocess. Microsystems, 2007
Proceedings of the 26th IEEE International Performance Computing and Communications Conference, 2007
Proceedings of the 25th International Conference on Computer Design, 2007
2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2004
Data Organization and Retrieval on Parallel Air Channels: Performance and Energy Issues.
Wirel. Networks, 2004
Des. Autom. Embed. Syst., 2004
Proceedings of the 2004 Design, 2004
2003
ACM Trans. Embed. Comput. Syst., 2003
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
2001
Proceedings of the 1st Java Virtual Machine Research and Technology Symposium, 2001
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001