José M. Valverde

According to our database1, José M. Valverde authored at least 11 papers between 1994 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
Voice-Controlled Assistance Device for Victims of Gender-Based Violence.
Proceedings of the Developments and Advances in Defense and Security, 2019

2010
A Family of Low-Voltage Bulk-Driven CMOS Continuous-Time CMFB Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

Single-pair bulk-driven CMOS input stage: A compact low-voltage analog cell for scaled technologies.
Integr., 2010

2009
Compact low-voltage rail-to-rail bulk-driven CMOS opamp for scaled technologies.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2000
1-V rail-to-rail operational amplifiers in standard CMOS technology.
IEEE J. Solid State Circuits, 2000

1997
Cork quality classification system using a unified image processing and fuzzy-neural network methodology.
IEEE Trans. Neural Networks, 1997

Programmable time-multiplexed switched-capacitor variable equalizer for arbitrary frequency response realizations.
IEEE J. Solid State Circuits, 1997

1996
VERDI: an acoustically programmable and adjustable CMOS mixed-mode signal processor for hearing aid applications.
IEEE J. Solid State Circuits, 1996

1995
Biasing circuit for high input swing operational amplifiers.
IEEE J. Solid State Circuits, February, 1995

A Class of Fully-Differential Basic Building Blocks Based on Unity-Gain Differnence Feedback.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
An Improved Biasing Circuit for High Input CMR Op Amps.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994


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