Gunhee Han

According to our database1, Gunhee Han authored at least 49 papers between 1995 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
A Fully Digital Time-Mode CMOS Image Sensor with 22.9pJ/frame.pixel and 92dB Dynamic Range.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2019
An Adaptive Shuttering Scheme for Speed-Artifact-Free Swipe Fingerprint Sensor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Effects of using a second-screen application on attention, learning, and user experience in an educational content.
Interact. Learn. Environ., 2018

2017
Bio-impedance analysis for high-speed and wide-band application by using pulse stimulation.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

23.8 A 1V 7.8mW 15.6Gb/s C-PHY transceiver using tri-level signaling for post-LPDDR4.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

An area/power efficient electrode-matched neural-spike detector embedded in implantable 256-channel MEA.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2015
A 2 mW, 50 dB DR, 10 MHz BW 5 × Interleaved Bandpass Delta-Sigma Modulator at 50 MHz IF.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Bulk Switching Instrumentation Amplifier for a High-Impedance Source in Neural Signal Recording.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Gaze-Assisted User Intention Prediction for Initial Delay Reduction in Web Video Access.
Sensors, 2015

Analysis of 1/ƒ<sup>2</sup> and 1/ƒ<sup>3</sup> noise in the high-pass chopper amplifier with a high-impedance source.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

A second screen web service framework based on multimedia package distribution.
Proceedings of the IEEE International Conference on Consumer Electronics, 2015

2014
A Current Regulator for Inverter-Based Massively Column-Parallel ΔΣ ADCs.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

2011
A 240-frames/s 2.1-Mpixel CMOS Image Sensor With Column-Shared Cyclic ADCs.
IEEE J. Solid State Circuits, 2011

A 2.1 M Pixels, 120 Frame/s CMOS Image Sensor With Column-Parallel Delta Sigma ADC Architecture.
IEEE J. Solid State Circuits, 2011

2010
An 8.5-Gb/s Fully Integrated CMOS Optoelectronic Receiver Using Slope-Detection Adaptive Equalizer.
IEEE J. Solid State Circuits, 2010

An 8.5Gb/s CMOS OEIC with on-chip photodiode for short-distance optical communications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 2.1Mpixel 120frame/s CMOS image sensor with column-parallel ΔΣ ADC architecture.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
A 200µs Processing Time Smart Image Sensor for an Eye Tracker Using Pixel-Level Analog Image Processing.
IEEE J. Solid State Circuits, 2009

Low Voltage, Low Power, Inverter-Based Switched-Capacitor Delta-Sigma Modulator.
IEEE J. Solid State Circuits, 2009

Mismatch-Insensitive High Precision Switched-Capacitor Multiply-by-Four Amplifier.
IEICE Trans. Electron., 2009

An Offset Cancelled Winner-Take-All Circuit.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

2008
Noise Analysis and Simulation Method for a Single-Slope ADC With CDS in a CMOS Image Sensor.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

A 5000S/s Single-Chip Smart Eye-Tracking Sensor.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 0.7V 36μW 85dB-DR Audio ΔΣ Modulator Using Class-C Inverter.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
An <i>I/Q</i>-Channel Time-Interleaved Bandpass Sigma-Delta Modulator for a Low-IF Receiver.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

A pixel array PSD with divide-by-M winner-take-all architecture.
IEICE Electron. Express, 2007

A 1.5V mixed signal biomedical SOC for implantable cardioverter defibrillators.
Proceedings of the 2007 IEEE International SOC Conference, 2007

A 1.2V 5.2mW 40dB 2.5Gb/s Limiting Amplifier in 0.18μm CMOS Using Negative-Impedance Compensation.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

An I/Q Channel Time-Interleaved Band-Pass Sigma-Delta Modulator for a Low-IF Receiver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Low Power Dual-Mode Sigma-Delta Modulator for GSM/WCDMA Receivers.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

A Low Noise and Low Power CMOS Image Sensor with Pixel-level Correlated Double Sampling.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006
Convergence analysis of the cascade second-order adaptive line equalizer.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

A Compact Implementation Scheme of 1-Dimensional PSDs with Double-Resolution Interpolation.
IEICE Trans. Electron., 2006

1lambda-Deviation Compensation Scheme for Ultrasonic Positioning System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

An adaptation method for FIR pre-emphasis filter on backplane channel.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

CMOS image sensor with analog gamma correction using nonlinear single-slope ADC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 5.2-mW, 2.5-Gb/s Limiting Amplifer for OC-48 SONET Applications.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
A time-interleaved recursive loop band-pass delta-sigma modulator for a digital IF CDMA receiver.
IEEE Trans. Circuits Syst. II Express Briefs, 2005

Sub-µW Switched-Capacitor Circuits Using a Class-C Inverter.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

A SIMD Neural Network Processor for Image Processing.
Proceedings of the Advances in Neural Networks - ISNN 2005, Second International Symposium on Neural Networks, Chongqing, China, May 30, 2005

2004
Code-width testing-based compact ADC BIST circuit.
IEEE Trans. Circuits Syst. II Express Briefs, 2004

New distributed arithmetic algorithm for low-power FIR filter implementation.
IEEE Signal Process. Lett., 2004

An Acceleration Processor for Data Intensive Scientific Computing.
IEICE Trans. Inf. Syst., 2004

A 0.8-µW switched-capacitor sigma-delta modulator using a class-C inverter.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
A time-interleaved switched-capacitor band-pass delta-sigma modulator.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2001
Multigradient: a new neural network learning algorithm for pattern classification.
IEEE Trans. Geosci. Remote. Sens., 2001

1999
CMOS cryptosystem using a Lorenz chaotic oscillator.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1997
Cork quality classification system using a unified image processing and fuzzy-neural network methodology.
IEEE Trans. Neural Networks, 1997

1995
A General Purpose Discrete-Time Multiplexing Neuron-Array Architecture.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995


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