José Oliver

Affiliations:
  • Technical University of Catalonia, Computer Architecture Department, Barcelona, Spain


According to our database1, José Oliver authored at least 8 papers between 2000 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Accelerating SpMV on FPGAs Through Block-Row Compress: A Task-Based Approach.
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

b8c: SpMV accelerator implementation leveraging high memory bandwidth.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

2001
New OpenMP directives for irregular data access loops.
Sci. Program., 2001

Strategies for the efficient exploitation of loop-level parallelism in Java.
Concurr. Comput. Pract. Exp., 2001

2000
NanosCompiler: supporting flexible multilevel parallelism exploitation in OpenMP.
Concurr. Pract. Exp., 2000

OpenMP Extensions for Thread Groups and Their Run-Time Support.
Proceedings of the Languages and Compilers for Parallel Computing, 2000

Towards an efficient exploitation of loop-level parallelism in Java.
Proceedings of the ACM 2000 Java Grande Conference, San Francisco, CA, USA, 2000

Applying Interposition Techniques for Performance Analysis of OpenMP Parallel Applications.
Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), 2000


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