Teresa Cervero

Orcid: 0000-0001-7535-4821

Affiliations:

Barcelona Supercomputing Center, Barcelona, Spain

According to our database¹, Teresa Cervero authored at least 19 papers between 2011 and 2026.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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Book In proceedings Article PhD thesis Dataset Other

Bibliography

2026

Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL.

[BibT_eX]

[DOI]

CoRR, April, 2026

Multi Partner Project: STRATUM, co-creation protocol and advanced smart GUI for a 3D neurosurgery supporting tool.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference, 2026

2025

Memory Sandbox 2.0: A Framework for Enabling HBM2e vs HBM2 Performance and Telemetry Analysis on Xilinx FPGAs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Memory Systems, 2025

2024

Memory Sandbox: A Versatile Tool for Analyzing and Optimizing HBM Performance in FPGA.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International Symposium on Computer Architecture and High Performance Computing, 2024

Makinote: An FPGA-Based HW/SW Platform for Pre-Silicon Emulation of RISC-V Designs.

[BibT_eX]

[DOI]

Elias Perdomo

Alexander Kropotov

Francelly Katherine Cano Ladino

Syed Zafar

Teresa Cervero

Xavier Martorell Bofill

Behzad Salami

Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design, 2024

3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project.

[BibT_eX]

[DOI]

Proceedings of the 27th Euromicro Conference on Digital System Design, 2024

2023

Optimizations for Very Long and Sparse Vector Operations on a RISC-V VPU: A Work-in-Progress.

[BibT_eX]

[DOI]

Proceedings of the High Performance Computing, 2023

Accelerating SpMV on FPGAs Through Block-Row Compress: A Task-Based Approach.

[BibT_eX]

[DOI]

Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

b8c: SpMV accelerator implementation leveraging high memory bandwidth.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

Ethernet Emulation over PCIe for RISC-V Software Development Vehicles.

[BibT_eX]

[DOI]

Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

2016

A scalable H.264/AVC deblocking filter architecture.

[BibT_eX]

[DOI]

J. Real Time Image Process., 2016

2015

A Scalable and Dynamically Reconfigurable FPGA-Based Embedded System for Real-Time Hyperspectral Unmixing.

[BibT_eX]

[DOI]

IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2015

2014

Dynamically reconfigurable architectures for video coding and hyperspectral imaging systems.

[BibT_eX]

[DOI]

Teresa Cervero

PhD thesis, 2014

Scalable architectures for real-time hyperspectral unmixing.

[BibT_eX]

[DOI]

Microelectron. J., 2014

2013

A Resource Manager for Dynamically Reconfigurable FPGA-Based Embedded Systems.

[BibT_eX]

[DOI]

Fernando Rincón Calle

Roberto Sarmiento

Juan Carlos López

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012

A Modular-Based Assembly Framework for Autonomous Reconfigurable Systems.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011

Scalable Models for Autonomous Self-Assembled Reconfigurable Systems.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

A novel scalable Deblocking Filter architecture for H.264/AVC and SVC video codecs.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Conference on Multimedia and Expo, 2011

Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Teresa Cervero

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Bibliography

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