Teresa Cervero

Orcid: 0000-0001-7535-4821

Affiliations:
  • Barcelona Supercomputing Center, Barcelona, Spain


According to our database1, Teresa Cervero authored at least 13 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2024
Makinote: An FPGA-Based HW/SW Platform for Pre-Silicon Emulation of RISC-V Designs.
Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design, 2024

2023
Optimizations for Very Long and Sparse Vector Operations on a RISC-V VPU: A Work-in-Progress.
Proceedings of the High Performance Computing, 2023

Accelerating SpMV on FPGAs Through Block-Row Compress: A Task-Based Approach.
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

b8c: SpMV accelerator implementation leveraging high memory bandwidth.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

Ethernet Emulation over PCIe for RISC-V Software Development Vehicles.
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

2016
A scalable H.264/AVC deblocking filter architecture.
J. Real Time Image Process., 2016

2015
A Scalable and Dynamically Reconfigurable FPGA-Based Embedded System for Real-Time Hyperspectral Unmixing.
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2015

2014
Scalable architectures for real-time hyperspectral unmixing.
Microelectron. J., 2014

2013
A Resource Manager for Dynamically Reconfigurable FPGA-Based Embedded Systems.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
A Modular-Based Assembly Framework for Autonomous Reconfigurable Systems.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011
Scalable Models for Autonomous Self-Assembled Reconfigurable Systems.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

A novel scalable Deblocking Filter architecture for H.264/AVC and SVC video codecs.
Proceedings of the 2011 IEEE International Conference on Multimedia and Expo, 2011

Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011


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