John D. Davis

Orcid: 0000-0003-0266-0857

According to our database1, John D. Davis authored at least 36 papers between 1998 and 2023.

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Bibliography

2023
Optimizations for Very Long and Sparse Vector Operations on a RISC-V VPU: A Work-in-Progress.
Proceedings of the High Performance Computing, 2023

Accelerating SpMV on FPGAs Through Block-Row Compress: A Task-Based Approach.
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

b8c: SpMV accelerator implementation leveraging high memory bandwidth.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

Ethernet Emulation over PCIe for RISC-V Software Development Vehicles.
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

2021
The MareNostrum Experimental Exascale Platform (MEEP).
Supercomput. Front. Innov., 2021

Coyote: An Open Source Simulation Tool to Enable RISC- V in HPC.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2015
Confident difference criterion: a new Bayesian differentially expressed gene selection algorithm with applications.
BMC Bioinform., 2015

Purity: Building Fast, Highly-Available Enterprise Flash Storage from Commodity Components.
Proceedings of the 2015 ACM SIGMOD International Conference on Management of Data, Melbourne, Victoria, Australia, May 31, 2015

2014
Star-Cap: Cluster Power Management Using Software-Only Models.
Proceedings of the 43rd International Conference on Parallel Processing Workshops, 2014

2013
CORFU: A distributed shared log.
ACM Trans. Comput. Syst., 2013

The Harey Tortoise: Managing Heterogeneous Write Performance in SSDs.
Proceedings of the 2013 USENIX Annual Technical Conference, 2013

Beyond block I/O: implementing a distributed shared log in hardware.
Proceedings of the 6th Annual International Systems and Storage Conference, 2013

Tango: distributed data structures over a shared log.
Proceedings of the ACM SIGOPS 24th Symposium on Operating Systems Principles, 2013

LINQits: big data on little clients.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

Zombie memory: extending memory lifetime by reviving dead blocks.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

Flash trends: Challenges and future.
Proceedings of the 2013 IEEE Hot Chips 25 Symposium (HCS), 2013

2012
From paxos to CORFU: a flash-speed shared log.
ACM SIGOPS Oper. Syst. Rev., 2012

CORFU: A Shared Log Design for Flash Clusters.
Proceedings of the 9th USENIX Symposium on Networked Systems Design and Implementation, 2012

CHAOS: Composable Highly Accurate OS-based power models.
Proceedings of the 2012 IEEE International Symposium on Workload Characterization, 2012

Towards a Universal FPGA Matrix-Vector Multiplication Architecture.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

The bleak future of NAND flash memory.
Proceedings of the 10th USENIX conference on File and Storage Technologies, 2012

2010
BLAS Comparison on FPGA, CPU and GPU.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

WiDGET: Wisconsin decoupled grid execution tiles.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

The Search for Energy-Efficient Building Blocks for the Data Center.
Proceedings of the Computer Architecture, 2010

Depletable Storage Systems.
Proceedings of the 2nd USENIX Workshop on Hot Topics in Storage and File Systems, 2010

2009
Block Management in Solid-State Devices.
Proceedings of the 2009 USENIX Annual Technical Conference, 2009

Tuning SoCs using the global dynamic critical path.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

2008
Design Tradeoffs for SSD Performance.
Proceedings of the 2008 USENIX Annual Technical Conference, 2008

Designing an Efficient Hardware Implication Accelerator for SAT Solving.
Proceedings of the Theory and Applications of Satisfiability Testing, 2008

Polymorphic On-Chip Networks.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

A practical reconfigurable hardware accelerator for Boolean satisfiability solvers.
Proceedings of the 45th Design Automation Conference, 2008

2005
A chip prototyping substrate: the flexible architecture for simulation and testing (FAST).
SIGARCH Comput. Archit. News, 2005

The RASE (Rapid, Accurate Simulation Environment) for chip multiprocessors.
SIGARCH Comput. Archit. News, 2005

Maximizing CMP Throughput with Mediocre Cores.
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 2005

2004
Transactional Memory Coherence and Consistency.
Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004

1998
A graphical tool for ad hoc query generation.
Proceedings of the AMIA 1998, 1998


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