Juan Carlos Diaz

According to our database, Juan Carlos Diaz authored at least 6 papers between 1995 and 1999.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

1999

The μPP ASIC: design, methodologies and tools for a pay phone system-on-a-chip based on an ARM core and design reuse.

Jacobo Riesco, Juan Carlos Diaz, Pierre Plaza

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1998

FPGA Implementation of an ATM Traffic Shaper: ATS (Abstract).

Jesus Crespo, Juan Carlos Diaz, Pimitivo Matas

Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

ATM Traffic Shaper: ATS.

Juan Carlos Diaz, Pierre Plaza, Jesus Crespo

Proceedings of the 1998 Design, 1998

1997

On the way to the 2.5 Gbits/s ATM network ATM multiplexer demultiplexer ASIC.

Jacobo Riesco, Juan Carlos Diaz, Luis A. Merayo, José Luis Conesa, Carlos Santos, Eduardo Juárez Martínez

Proceedings of the European Design and Test Conference, 1997

1996

A 2.5 Gb/s ATM switch chip set.

Pierre Plaza, Luis A. Merayo, Juan Carlos Diaz, José Luis Conesa

IEEE Trans. Very Large Scale Integr. Syst., 1996

1995

Input and output processor for an ATM high speed switch (2.5 Gb/s): the CMC.

Pierre Plaza, Juan Carlos Diaz, Fermín Calvo, Luis A. Merayo, Maurizio Zamboni, Pietro Scarfone, Marco Barbini

Proceedings of the 1995 European Design and Test Conference, 1995