Juan Pablo Martinez Brito

According to our database1, Juan Pablo Martinez Brito authored at least 9 papers between 2007 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2014
A 2-Transistor Sub-1V Low Power Temperature Compensated CMOS Voltage Reference.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

A low-power RF/analog front-end architecture for LF passive RFID tags with dynamic power sensing.
Proceedings of the IEEE International Conference on RFID, 2014

A power management system architecture for LF passive RFID tags.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

2013
Low-Power/Low-Voltage analog front-end for LF passive RFID tag systems.
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

CMOS smart temperature sensors for RFID applications.
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

2009
A DC offset and CMRR analysis in a CMOS 0.35 µm operational transconductance amplifier using Pelgrom's area/accuracy tradeoff.
Microelectron. J., 2009

2007
Design of a digital FM demodulator based on a 2nddegree order all-digital phase-locked loop.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

A Design Methodology for Matching Improvement in Bandgap References.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

A 4-Bits Trimmed CMOS Bandgap Reference with an Improved Matching Modeling Design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007


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