Sergio Bampi

Leandro Mateus Giacomini Rocha

Gustavo Madeira Santana

Eduardo Antonio Cesar da Costa

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Wideband Low-Noise Variable-Gain Amplifier With a 3.4 dB NF and up to 45 dB Gain Tuning Range in 130-nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2019

Energy-aware cache hierarchy assessment targeting HEVC encoder execution.

[BibT_eX]

[DOI]

J. Real Time Image Process., 2019

Improving devices communication in Industry 4.0 wireless networks.

[BibT_eX]

[DOI]

Eng. Appl. Artif. Intell., 2019

A sub-1mA highly linear inductorless wideband LNA with low IP3 sensitivity to variability for IoT applications.

[BibT_eX]

[DOI]

Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019

Energy Savings with Non-Volatile Memory System for High Definition Video Encoders.

[BibT_eX]

[DOI]

Dieison Soares Silveira

Ana Mativi

Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

Maximizing the Power-Efficiency of the Approximate Pruned Modified Rounded DCT Exploiting Approximate Adder Compressors.

[BibT_eX]

[DOI]

Eduardo Antônio César da Costa

Leandro M. G. Rocha

Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

Exploring Motion Vector Cost with Partial Distortion Elimination in Sum of Absolute Differences for HEVC Integer Motion Estimation.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

HEVC Interpolation Filter Architecture Using Hybrid Encoding Arithmetic Operators.

[BibT_eX]

[DOI]

Rafael S. Ferreira

Brunno A. Abreu

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing.

[BibT_eX]

[DOI]

Vitor G. Lima

Leandro M. G. Rocha

Leomar S. da Rosa Jr.

Felipe S. Marques

Vinicius V. Camargo

Rafael Soares

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A 300mV-Supply, 2nW-Power, 80pF-Load CMOS Digital-Based OTA for IoT Interfaces.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Approximate Sum of Absolute Transformed Differences Hardware Accelerator.

[BibT_eX]

[DOI]

Matheus F. Stigger

Victor H. S. Lima

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

A Configurable Pruning Gaussian Image Filter for Energy-Efficient Edge Detection.

[BibT_eX]

[DOI]

Eduardo Antônio César da Costa

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

A 0.6 V Current Reference Based on the MOSFET Forward-Body-Biased ZTC Condition.

[BibT_eX]

[DOI]

Luis Henrique Rodovalho

Pedro Toledo

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Exploring Architectural Solutions for an Energy-Efficient Kalman Filter Gain Realization.

[BibT_eX]

[DOI]

Pedro Tauã Lopes Pereira

Patrícia Ücker

Leandro Mateus Giacomini Rocha

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Low power 380μW Energy Efficient 1.8 GHz Digitally Controlled Oscillator for IoT Applications.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Real-time HR Estimation from wrist PPG using Binary LSTMs.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

2018

A 0.12-0.4 V, Versatile 3-Transistor CMOS Voltage Reference for Ultra-Low Power Systems.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

40-nm CMOS Wideband High-IF Receiver Using a Modified Charge-Sharing Bandpass Filter to Boost Q-Factor.

[BibT_eX]

[DOI]

Filipe D. Baumgratz

Sandro Binsfeld Ferreira

Michiel S. J. Steyaert

Filip Tavernier

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Improving network resources allocation in smart cities video surveillance.

[BibT_eX]

[DOI]

Comput. Networks, 2018

A Charge-Sharing Bandpass Filter Topology with Boosted Q-Factor in 40-NM CMOS.

[BibT_eX]

[DOI]

Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

Exploiting Partial Distortion Elimination in the Sum of Absolute Differences for Energy-Efficient HEVC Integer Motion Estimation.

[BibT_eX]

[DOI]

Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

A Fixed-Point Natural Logarithm Approximation Hardware Design Using Taylor Series.

[BibT_eX]

[DOI]

Miguel R. Weirich

Proceedings of the 2018 New Generation of CAS, 2018

Low-Power HEVC 8-point 2-D Discrete Cosine Transform Hardware Using Adder Compressors.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

Exploring power-performance-quality tradeoff of approximate adders for energy efficient sobel filtering.

[BibT_eX]

[DOI]

Morgana M. A. da Rosa

Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

High-Throughput Binary Arithmetic Encoder using Multiple-Bypass Bins Processing for HEVC CABAC.

[BibT_eX]

[DOI]

Alessandro Via Piana Saggiorato

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Exploring the Impact of Soft Errors on NoC-based Multiprocessor Systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

HEVC Residual Syntax Elements Generation Architecture for High-Throughput CABAC Design.

[BibT_eX]

[DOI]

Luís Alberto da Silva Cruz

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Learning-Based Complexity Reduction and Scaling for HEVC Encoders.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Conference on Acoustics, 2018

2017

Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Picowatt, 0.45-0.6 V Self-Biased Subthreshold CMOS Voltage Reference.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Complexity control of HEVC encoders targeting real-time constraints.

[BibT_eX]

[DOI]

J. Real Time Image Process., 2017

Novel multiple bypass bins scheme for low-power UHD video processing HEVC binary arithmetic encoder architecture.

[BibT_eX]

[DOI]

Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

A power-predictive environment for fast and power-aware ASIC-based FIR filter design.

[BibT_eX]

[DOI]

Rafael S. Ferreira

Leandro M. G. Rocha

Tiago Giacomelli Alves

Luana Vieira Martinez Bonatto

Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

Estimation methods for static noise margins in CMOS subthreshold logic circuits.

[BibT_eX]

[DOI]

Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

Low-power multi-size HEVC DCT architecture proposal for QFHD video processing.

[BibT_eX]

[DOI]

Gabriel Teofilo Neves Guimaraes

Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

Low power IEEE 802.11ah receiver system-level design aiming for IoT applications.

[BibT_eX]

[DOI]

Nelson Andrade

Pedro Toledo

Helga Dornelas

Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

Low-power HEVC binarizer architecture for the CABAC block targeting UHD video processing.

[BibT_eX]

[DOI]

Camila de Matos Alonso

Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

Pruning and approximation of coefficients for power-efficient 2-D Discrete Tchebichef Transform.

[BibT_eX]

[DOI]

Rafael S. Ferreira

Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

An ultra-low power high-order temperature- compensated CMOS voltage reference.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Data compression and decompression Integrated Circuit for AC Power Quality data.

[BibT_eX]

[DOI]

Marcos Hervé

Cristiano Thiele

Diogenes Machado

Guilherme Wojichowski

César Crovato

Gabriel Teofilo Neves Guimaraes

Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

A fully integrated CMOS 2.4GHz and 24dBm linear power amplifier.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

A power-efficient 4-2 Adder Compressor topology.

[BibT_eX]

[DOI]

Roger Luis Brito Zamparette

Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

A 90% efficiency 60 mW MPPT switched capacitor DC - DC converter for photovoltaic energy harvesting aiming for IoT applications.

[BibT_eX]

[DOI]

Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

A 0.45 V, 93 pW temperature-compensated CMOS voltage reference.

[BibT_eX]

[DOI]

Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

A high IIP3 6.5 mW self-biased 0.3-3 GHz small area LNA.

[BibT_eX]

[DOI]

Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

A sub-1 V, nanopower, ZTC based zero-VT temperature-compensated current reference.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Using adder and subtractor compressors to sum of absolute transformed differences architecture for low-power video encoding.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Exploring the combination of number of bits and number of iterations for a power-efficient fixed-point CORDIC implementation.

[BibT_eX]

[DOI]

Andre N. Sapper

Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Using efficient adder compressors with a split-radix butterfly hardware architecture for low-power IoT smart sensors.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Physical implementation of an ASIC-oriented SRAM-based viterbi decoder.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Framework-based arithmetic core generation to explore ASIC-based parallel binary multipliers.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Improved goldschmidt algorithm for fast and energy-efficient fixed-point divider.

[BibT_eX]

[DOI]

Pedro Marques

Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Exploiting absolute arithmetic for power-efficient sum of absolute differences.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Performance and energy consumption analysis of the X265 video encoder.

[BibT_eX]

[DOI]

Dieison Silveira

Proceedings of the 25th European Signal Processing Conference, 2017

2016

Improving QoS in multi-operator cellular networks.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on Wireless and Mobile Computing, 2016

A 0.7V Fully Differential First Order GZTC-C filter.

[BibT_eX]

[DOI]

Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

A novel pruned-based algorithm for energy-efficient SATD operation in the HEVC coding.

[BibT_eX]

[DOI]

Eduardo Antonio Cesar da Costa

Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

Low-power hardware design for the HEVC Binary Arithmetic Encoder targeting 8K videos.

[BibT_eX]

[DOI]

Jones Goebel

Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

A 450 mV supply self-biased wideband inductorless balun LNA for sub-GHz applications.

[BibT_eX]

[DOI]

Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

A 0.3 V, high-PSRR, picowatt NMOS-only voltage reference using zero-VT active loads.

[BibT_eX]

[DOI]

Felipe Todeschini Bortolon

Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

Design and analysis of the HF-RISC processor targeting voltage scaling applications.

[BibT_eX]

[DOI]

Sergio Johann Filho

Matheus Gibiluka

Ney Laert Vilar Calazans

Fabiano Passuelo Hessel

Matheus Trevisan Moreira

Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

Complexity-scalable HEVC encoding.

[BibT_eX]

[DOI]

Mateus Grellert

Proceedings of the 2016 Picture Coding Symposium, 2016

Adjusting video tiling to available resources in a per-frame basis in High Efficiency Video Coding.

[BibT_eX]

[DOI]

Giovani Malossi

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

A Resources Sharing Architecture for Heterogeneous Wireless Cellular Networks.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE Conference on Local Computer Networks, 2016

Nano-watt 0.3 V supply resistorless voltage reference with Schottky diode.

[BibT_eX]

[DOI]

Renato Campana V.

Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

CMOS RF class-E power amplifier with power control.

[BibT_eX]

[DOI]

Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Exploiting approximate adder circuits for power-efficient Gaussian and Gradient filters for Canny edge detector algorithm.

[BibT_eX]

[DOI]

Julio de Oliveira

Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

0.3 V supply, 17 ppm/°C 3-transistor picowatt voltage reference.

[BibT_eX]

[DOI]

Jhon Gomez Caicedo

Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Memory access profiling for HEVC encoders.

[BibT_eX]

[DOI]

Ana Mativi

Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

A 90 dB PSRR, 4 dBm EMI resistant MOSFET-Only Voltage Reference.

[BibT_eX]

[DOI]

Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

1.5 ppm/°C nano-Watt resistorless MOS-only voltage reference.

[BibT_eX]

[DOI]

Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Energy-aware cache assessment of HEVC decoding.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Ultra-low voltage wideband inductorless balun LNA with high gain and high IP2 for sub-GHz applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Segmentation and classification of melanocytic skin lesions using local and contextual features.

[BibT_eX]

[DOI]

Eliezer Bernart

Jacob Scharcanski

Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

System energy analysis for shared memory multiprocessing applications.

[BibT_eX]

[DOI]

Dieison Soares Silveira

Eduardo Henrique Molina da Cruz

Gabriel B. Moro

Philippe O. A. Navaux

Lucas Mello Schnorr

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

A power-efficient imprecise radix-4 multiplier applied to high resolution audio processing.

[BibT_eX]

[DOI]

Julio F. R. Oliveira

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Energy efficiency evaluation of the pulse shapes and modulation techniques for IR-UWB in WBANs.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Memory energy consumption analyzer for video encoder hardware architectures.

[BibT_eX]

[DOI]

Lívia Amaral

Guilherme Povala

Dieison Silveira

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015

A Reconfigurable Hardware Architecture for Fractional Pixel Interpolation in High Efficiency Video Coding.

[BibT_eX]

[DOI]

Andre Luis Rodeghiero Rosa

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

CMOS Transconductor Analysis for Low Temperature Sensitivity Based on ZTC MOSFET Condition.

[BibT_eX]

[DOI]

Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

Designing CMOS for Near-Threshold Minimum-Energy Operation and Extremely Wide V-F Scaling.

[BibT_eX]

[DOI]

Kleber Hugo Stangherlin

Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

A 2-decades Wideband Low-Noise Amplifier with High Gain and ESD Protection.

[BibT_eX]

[DOI]

Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

0.5 V Supply Voltage Reference Based on the MOSFET ZTC Condition.

[BibT_eX]

[DOI]

Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

0.5 V Supply Resistorless Voltage Reference for Low Voltage Applications.

[BibT_eX]

[DOI]

Renato Campana V.

Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

Wideband Low Noise Variable Gain Amplifier.

[BibT_eX]

[DOI]

Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

Near-threshold computing for very wide frequency scaling: Approximate adders to rescue performance.

[BibT_eX]

[DOI]

Andre Luis Rodeghiero Rosa

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Approximate adder synthesis for area- and energy-efficient FIR filters in CMOS VLSI.

[BibT_eX]

[DOI]

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Enhancing a HEVC interpolation filter hardware architecture with efficient adder compressors.

[BibT_eX]

[DOI]

Mateus Beck Fonseca

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

EMI resisting MOSFET-Only Voltage Reference based on the ZTC condition.

[BibT_eX]

[DOI]

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Resistorless switched-capacitor current reference based on the MOSFET ZTC condition.

[BibT_eX]

[DOI]

Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

MOS-only M-2M DAC for ultra-low voltage applications.

[BibT_eX]

[DOI]

Israel Sperotto

Jeferson Santiago da Silva

Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Area-oriented iterative method for Design Space Exploration with High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Nanoscale FinFET global parameter extraction for the BSIM-CMG model.

[BibT_eX]

[DOI]

Alessandra Leonhardt

Luiz Fernando Ferreira

Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

A CMOS low noise transconductance amplifier for 1-6 GHz bands.

[BibT_eX]

[DOI]

Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

High compression ratio algorithm for power quality signals.

[BibT_eX]

[DOI]

Roque Eduardo Dapper

César David Paredes Crovato

Proceedings of the 24th IEEE International Symposium on Industrial Electronics, 2015

Rate-distortion and energy performance of HEVC and H.264/AVC encoders: A comparative analysis.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

0.7 V supply self-biased nanoWatt MOS-only threshold voltage monitor.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Effective device electrical parameter extraction of nanoscale FinFETs: Challenges and results.

[BibT_eX]

[DOI]

Alessandra Leonhardt

Luiz Fernando Ferreira

Leandro Tiago Manera

Proceedings of the 27th International Conference on Microelectronics, 2015

Area efficient and high throughput CABAC encoder architecture for HEVC.

[BibT_eX]

[DOI]

Volnei Mazui

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Design and linearity analysis of a M-2M DAC for very low supply voltage.

[BibT_eX]

[DOI]

Israel Sperotto

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

A power controlled RF CMOS class-E PA with 43% maximum efficiency in 2.2 GHz.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Energy-efficient Gaussian filter for image processing using approximate adder circuits.

[BibT_eX]

[DOI]

Julio F. R. Oliveira

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

A deblocking filter hardware architecture for the high efficiency video coding standard.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Approximation-aware Multi-Level Cells STT-RAM cache architecture.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Compilers, 2015

2014

Parallelization of Full Search Motion Estimation Algorithm for Parallel and Distributed Platforms.

[BibT_eX]

[DOI]

Marilena Maule

Moacir Fernandes Cortinhas Monteiro

Int. J. Parallel Program., 2014

Self-biased CMOS Current Reference based on the ZTC Operation Condition.

[BibT_eX]

[DOI]

Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

High Linearity and Large Output Swing Sub-Hz Pre-amplifier for Portable Biomedical Applications.

[BibT_eX]

[DOI]

Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

Sub-1 V Supply Nano-Watt MOSFET-Only Threshold Voltage Extractor Circuit.

[BibT_eX]

[DOI]

Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

A CMOS Down-Conversion Mixer with High IIP2 and IIP3 for Multi-Band and Multiple Standards.

[BibT_eX]

[DOI]

Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

Rate-distortion and energy performance of HEVC video encoders.

[BibT_eX]

[DOI]

Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

0.7 V supply, 8 nW, 8 ppm/°C resistorless sub-bandgap voltage reference.

[BibT_eX]

[DOI]

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

0.9 V, 5 nW, 9 ppm/oC resistorless sub-bandgap voltage reference in 0.18μm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Content-driven memory pressure balancing and video memory power management for parallel high efficiency video coding.

[BibT_eX]

[DOI]

Felipe Martin Sampaio

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

2.3 ppm/°c 40 nW MOSFET-only voltage reference.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Energy-efficient architecture for advanced video memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Run-time accelerator binding for tile-based mixed-grained reconfigurable architectures.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

dSVM: Energy-efficient distributed Scratchpad Video Memory Architecture for the next-generation High Efficiency Video Coding.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Model Predictive Hierarchical Rate Control With Markov Decision Process for Multiview Video Coding.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2013

Iterative random search: a new local minima resistant algorithm for motion estimation in high-definition videos.

[BibT_eX]

[DOI]

Cassio Cristani

Pargles Dall'Oglio

Mateus Grellert

Júlio C. B. de Mattos

Multim. Tools Appl., 2013

A reduced memory bandwidth and high throughput HDTV motion compensation decoder for H.264/AVC High 4: 2: 2 profile.

[BibT_eX]

[DOI]

Leandro M. de L. Silva

J. Real Time Image Process., 2013

Energy-speed exploration for very-wide range of dynamic V-F scaling.

[BibT_eX]

[DOI]

Kleber Stangherlin

Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

A resistorless switched bandgap voltage reference with offset cancellation.

[BibT_eX]

[DOI]

Moacir Fernandes Cortinhas Monteiro

Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

Adaptive content-based Tile partitioning algorithm for the HEVC standard.

[BibT_eX]

[DOI]

Proceedings of the 30th Picture Coding Symposium, 2013

61 pJ/sample near-threshold notch filter with pole-radius variation.

[BibT_eX]

[DOI]

Kleber Stangherlin

Jorge de Mello

Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

A resistorless switched bandgap reference topology.

[BibT_eX]

[DOI]

Moacir Fernandes Cortinhas Monteiro

Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

Voltage reference design using 1 V power supply in 0.13 µm CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

Content-adaptive reference frame compression based on intra-frame prediction for multiview video coding.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Image Processing, 2013

High-throughput interpolation hardware architecture with coarse-grained reconfigurable datapaths for HEVC.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Image Processing, 2013

RF system level design for a Spectrum Sensing Receiver.

[BibT_eX]

[DOI]

Filipe D. Baumgratz

Sandro B. Ferreira

Proceedings of the 20th IEEE International Conference on Electronics, 2013

A fast EMD-based technique for Power Quality signals decomposition, compression, and time-frequency analysis.

[BibT_eX]

[DOI]

César David Paredes Crovato

Proceedings of the 18th International Conference on Digital Signal Processing, 2013

Energy-efficient memory hierarchy for motion and disparity estimation in multiview video coding.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

3D Video Coding for Embedded Devices - Energy Efficient Algorithms and Architectures.

[BibT_eX]

[DOI]

Springer, ISBN: 978-1-4614-6758-8, 2013

2012

Low-Complexity Hierarchical Mode Decision Algorithms Targeting VLSI Architecture Design for the H.264/AVC Video Encoder.

[BibT_eX]

[DOI]

VLSI Design, 2012

DMPDS: A Fast Motion Estimation Algorithm Targeting High Resolution Videos and Its FPGA Implementation.

[BibT_eX]

[DOI]

Gustavo Sanchez

Int. J. Reconfigurable Comput., 2012

Algorithm and Hardware Design of a Fast Intra Frame Mode Decision Module for H.264/AVC Encoders.

[BibT_eX]

[DOI]

Int. J. Reconfigurable Comput., 2012

A low-cost and high efficiency entropy encoder architecture for H.264/AVC.

[BibT_eX]

[DOI]

Cristiano Thiele

André L. M. Martinez

Vagner Santos Da Rosa

Henrique Luiz Andrade Pimentel

Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

A 50MHz-lGHz wideband low noise amplifier in 130nm CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

A Model Predictive Controller for Frame-Level Rate Control in Multiview Video Coding.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Conference on Multimedia and Expo, 2012

Spread and Iterative Search: A High Quality Motion Estimation Algorithm for High Definition Videos and Its VLSI Design.

[BibT_eX]

[DOI]

Gustavo Sanchez

Proceedings of the 2012 IEEE International Conference on Multimedia and Expo, 2012

Motion Vectors Merging: Low Complexity Prediction Unit Decision Heuristic for the Inter-prediction of HEVC Encoders.

[BibT_eX]

[DOI]

Mateus Grellert

Júlio C. B. de Mattos

Proceedings of the 2012 IEEE International Conference on Multimedia and Expo, 2012

A memory aware and multiplierless VLSI architecture for the complete Intra Prediction of the HEVC emerging standard.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Conference on Image Processing, 2012

Real-time block matching motion estimation onto GPGPU.

[BibT_eX]

[DOI]

Marilena Maule

Proceedings of the 19th IEEE International Conference on Image Processing, 2012

Design of a capacitorless low-dropout voltage regulator with fast load regulation in 130nm CMOS.

[BibT_eX]

[DOI]

Antonio David Souza

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Keynote: "Design space exploration and run-time resource management in the embedded multi-core era".

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th Symposium on Embedded Systems for Real-time Multimedia, 2012

Adaptive power management of on-chip video memory for multiview video coding.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011

Two fast multi-point search algorithms for high quality motion estimation in high resolution videos.

[BibT_eX]

[DOI]

Diego Noble

Int. J. Inf. Technol. Commun. Convergence, 2011

An efficient ME architecture for high definition videos using the new MPDS algorithm.

[BibT_eX]

[DOI]

Gustavo Sanchez

Diego Noble

Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Applying CUDA Architecture to Accelerate Full Search Block Matching Algorithm for High Performance Motion Estimation in Video Encoding.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Symposium on Computer Architecture and High Performance Computing, 2011

A high throughput H.264/AVC intra-frame encoding loop architecture for HD1080p.

[BibT_eX]

[DOI]

Cristiano Thiele

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

SHBS: A heuristic for fast inter mode decision of H.264/AVC standard targeting VLSI design.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Conference on Multimedia and Expo, 2011

A multi-level dynamic complexity reduction scheme for multiview video coding.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Conference on Image Processing, 2011

A low-power memory architecture with application-aware power management for motion & disparity estimation in Multiview Video Coding.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Multi-level pipelined parallel hardware architecture for high throughput motion and disparity estimation in Multiview Video Coding.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Run-time adaptive energy-aware motion and disparity estimation in multiview video coding.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

2010

Efficient Dedicated Multiplication Blocks for 2's Complement Radix-2m Array Multipliers.

[BibT_eX]

[DOI]

Leandro Zafalon Pieper

José C. Monteiro

J. Comput., 2010

Timing and interface communication analysis of H.264/AVC encoder using SystemC model.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Fast forward and inverse transforms for the H.264/AVC standard using hierarchical adder compressors.

[BibT_eX]

[DOI]

João S. Altermann

Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Performance enhancement of H.264/AVC intra frame prediction hardware using efficient 4-2 and 5-2 adder-compressors.

[BibT_eX]

[DOI]

João S. Altermann

Alexsandro Cristovão Bonatto

Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

A 720p H.264/AVC decoder ASIC implementation for digital television set-top boxes.

[BibT_eX]

[DOI]

André Borin Soares

Adriano Renner

Leandro Max Silva

Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

An adaptive early skip mode decision scheme for multiview video coding.

[BibT_eX]

[DOI]

Proceedings of the Picture Coding Symposium, 2010

Power-aware complexity-scalable multiview video coding for mobile devices.

[BibT_eX]

[DOI]

Proceedings of the Picture Coding Symposium, 2010

Heterogeneous integration: Beyond CMOS - coping with variability at the end of the CMOS roadmap.

[BibT_eX]

[DOI]

Proceedings of the 11th Latin American Test Workshop, 2010

Gop structure adaptive to the video content for efficient H.264/AVC encoding.

[BibT_eX]

[DOI]

Jacob Scharcanski

Proceedings of the International Conference on Image Processing, 2010

High performance architectures for the arithmetic encoder of the H.264/AVC CABAC entropy coder.

[BibT_eX]

[DOI]

Leandro Max Silva

Proceedings of the 17th IEEE International Conference on Electronics, 2010

A high throughput CAVLC hardware architecture with parallel coefficients processing for HDTV H.264/AVC enconding.

[BibT_eX]

[DOI]

André Luís Del Mestre Martins

Proceedings of the 17th IEEE International Conference on Electronics, 2010

A low-cost hardware architecture binarizer design for the H.264/AVC CABAC entropy coding.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Conference on Electronics, 2010

Homogeneity and distortion-based intra mode decision architecture for H.264/AVC.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009

A DC offset and CMRR analysis in a CMOS 0.35 µm operational transconductance amplifier using Pelgrom's area/accuracy tradeoff.

[BibT_eX]

[DOI]

Microelectron. J., 2009

Techniques for Architecture Design for Binary Arithmetic Decoder Engines Based on Bitstream Flow Analysis.

[BibT_eX]

[DOI]

Dieison Antonello Deprá

Proceedings of the VLSI-SoC: Technologies for Systems Integration, 2009

Challenges and Emerging Technologies for System Integration beyond the End of the Roadmap of Nano-CMOS.

[BibT_eX]

[DOI]

Ricardo Reis

Proceedings of the VLSI-SoC: Technologies for Systems Integration, 2009

High performance and low cost architecture for H.264/AVC CAVLD targeting HDTV.

[BibT_eX]

[DOI]

Fábio I. Pereira

Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

High performance motion estimation architecture using efficient adder-compressors.

[BibT_eX]

[DOI]

André Silva

Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

A High Performance H.264 Deblocking Filter.

[BibT_eX]

[DOI]

Proceedings of the Advances in Image and Video Technology, Third Pacific Rim Symposium, 2009

A method for HW functional verification through HW/SW co-simulation in complex systems: H.264/AVC decoder as case study.

[BibT_eX]

[DOI]

Dieison Antonello Deprá

Proceedings of the 10th Latin American Test Workshop, 2009

Low Cost and Memoryless CAVLD Architecture for H.264/AVC Decoder.

[BibT_eX]

[DOI]

João Alberto Vortmann

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Hardware Design of the H.264/AVC Variable Block Size Motion Estimation for Real-Time 1080HD Video Encoding.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

A real time H.264/AVC intra frame prediction hardware architecture for HDTV 1080P video.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE International Conference on Multimedia and Expo, 2009

High throughput scalable Motion Compensation architecture for H.264/SVC video coding standard.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

Design flow for the generation of optimized FIR filters.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

Power efficient architecture for motion estimation using the QSDS-DIC algorithm.

[BibT_eX]

[DOI]

João S. Altermann

Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008

High throughput architecture for H.264/AVC motion compensation sample interpolator for HDTV.

[BibT_eX]

[DOI]

Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

Architectural design for the new QSDS with dynamic iteration control motion estimation algorithm targeting HDTV.

[BibT_eX]

[DOI]

Luciano Severino de Paula

Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

A wide band CMOS differential voltage-controlled ring oscillator.

[BibT_eX]

[DOI]

Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

A novel hardware architecture design for binary arithmetic decoder engines based on bitstream flow analysis.

[BibT_eX]

[DOI]

Dieison Antonello Deprá

Vagner Santos Da Rosa

Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

A 40mhz 70db gain variable gain amplifier design using the gm/id design method.

[BibT_eX]

[DOI]

Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

Early voltage and saturation voltage improvement in deep sub-micron technologies using associations of transistors.

[BibT_eX]

[DOI]

Eduardo Conrad Jr.

Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

HP422-MoCHA: A H.264/AVC High Profile motion compensation architecture for HDTV.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A high throughput and low cost diamond search architecture for HDTV motion estimation.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Conference on Multimedia and Expo, 2008

2007

Multiplierless and fully pipelined JPEG compression soft IP targeting FPGAs.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2007

Design and FPGA Prototyping of a H.264/AVC Main Profile.

[BibT_eX]

[DOI]

Arnaldo P. Azevedo Filho

Wagston T. Staehler

Ana Cristina Medina Pinto

J. Braz. Comput. Soc., 2007

A new array architecture for signed multiplication using Gray encoded radix-2m operands.

[BibT_eX]

[DOI]

Integr., 2007

An HDTV H.264 deblocking filter in FPGA with RGB video output.

[BibT_eX]

[DOI]

Proceedings of the IFIP VLSI-SoC 2007, 2007

A fully integrated CMOS RF front-end for a multi-band analog mixed-signal interface.

[BibT_eX]

[DOI]

Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

Trim range limited by noise in bandgap voltage references.

[BibT_eX]

[DOI]

Dalton M. Colombo

Gilson I. Wirth

Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

Design of a digital FM demodulator based on a 2nddegree order all-digital phase-locked loop.

[BibT_eX]

[DOI]

Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

FPGA Prototyping Strategy for a H.264/AVC Video Decoder.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

Motion Compensation Hardware Accelerator Architecture for H.264/AVC.

[BibT_eX]

[DOI]

Valter Ferreira

Flávio Rech Wagner

Proceedings of the Advances in Image and Video Technology, Second Pacific Rim Symposium, 2007

A Pipelined 8x8 2-D Forward DCT Hardware Architecture for H.264/AVC High Profile Encoder.

[BibT_eX]

[DOI]

João Alberto Vortmann

Proceedings of the Advances in Image and Video Technology, Second Pacific Rim Symposium, 2007

High Throughput Hardware Architecture for Motion Estimation with 4: 1 Pel Subsampling Targeting Digital Television Applications.

[BibT_eX]

[DOI]

Leandro Rosa

Proceedings of the Advances in Image and Video Technology, Second Pacific Rim Symposium, 2007

Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder.

[BibT_eX]

[DOI]

Luciano Severino de Paula

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

A High Swing Low Power CMOS Differential Voltage-Controlled Ring Oscillator.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

A Design Methodology for Matching Improvement in Bandgap References.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

A 4-Bits Trimmed CMOS Bandgap Reference with an Improved Matching Modeling Design.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

MoCHA: a Bi-Predictive Motion Compensation Hardware for H.264/AVC Decoder Targeting HDTV.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

High Throughput Architecture for Forward Transforms Module of H.264/AVC Video Coding Standard.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on Electronics, 2007

A 1.4GHz Upconversion Mixer Design Using the gm/ID Method Suitable for a Multi-Band Analog Interface.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on Electronics, 2007

Impact of Noise on Trim Circuits for Bandgap Voltage References.

[BibT_eX]

[DOI]

Dalton Martini Colombo

Gilson Inácio Wirth

Christian Jesús B. Fayomi

Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006

Architecture of an HDTV Intraframe Predictor for a H.264 Decoder.

[BibT_eX]

[DOI]

Wagston T. Staehler

Eduardo A. Berriel

Proceedings of the IFIP VLSI-SoC 2006, 2006

A VHDL Generation Tool for Optimized Parallel FIR Filters.

[BibT_eX]

[DOI]

Proceedings of the IFIP VLSI-SoC 2006, 2006

Motion Compensation Decoder Architecture for H.264/AVC Main Profile Targeting HDTV.

[BibT_eX]

[DOI]

Proceedings of the IFIP VLSI-SoC 2006, 2006

Power constrained design optimization of analog circuits based on physical gm/ID characteristics.

[BibT_eX]

[DOI]

Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

A band-pass Gm-C Filter design based on gm/ID methodology and characterization.

[BibT_eX]

[DOI]

Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

A High Performance Parallel FIR Filters Generation Tool.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 2006

A tool for automatic design of analog circuits based on gm/ID methodology.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Reconfigurable analog interface for mixed signal SOC.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

High throughput multitransform and multiparallelism IP for H.264/AVC video compression standard.

[BibT_eX]

[DOI]

José Luís Güntzel

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Track-and-Latch Comparator Design Using Associations of MOS Transistors and Characterization.

[BibT_eX]

[DOI]

Fernando Paixão Cortes

Proceedings of the 13th IEEE International Conference on Electronics, 2006

High Throughput Architecture of JPEG Compressor for Color Images Targeting FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Electronics, 2006

High throughput architecture for H.264/AVC forward transforms block.

[BibT_eX]

[DOI]

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

FPGA Based Architectures for H. 264/AVC Video Compression Standard.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

FPGA Design of A H.264/AVC Main Profile Decoder for HDTV.

[BibT_eX]

[DOI]

Eduardo A. Berriel

Leonardo Londero de Oliveira

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005

A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures.

[BibT_eX]

[DOI]

Cristiano Santos

Daniel Lima Ferrão

João Baptista dos Santos Martins

Ricardo Augusto da Luz Reis

Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

T-shaped association of transistors: modeling of multiple channel lengths and regular associations.

[BibT_eX]

[DOI]

Eduardo Conrad Jr.

Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Design of a radix-2m hybrid array multiplier using carry save adder format.

[BibT_eX]

[DOI]

Mateus Fonseca

Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Reusing Traces in a Dynamic Conditional Execution Architecture.

[BibT_eX]

[DOI]

Philippe Olivier Alexandre Navaux

Proceedings of the 17th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2005), 2005

Accelerating a Multiprocessor Reconfigurable Architecture with Pipelined VLIW Units.

[BibT_eX]

[DOI]

Flávio Rech Wagner

Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

A FPGA Based Design of a Multiplierless and Fully Pipelined JPEG Compressor.

[BibT_eX]

[DOI]

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

Area and Throughput Trade-Offs in the Design of Pipelined Discrete Wavelet Transform Architectures.

[BibT_eX]

[DOI]

Sandro V. Silva

Proceedings of the 2005 Design, 2005

2004

AC analysis of an inverter amplifier using minimum-length trapezoidal association of transistors.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2004

Analysis and design of amplifiers and comparators in CMOS 0.35 mum technology.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2004

Parallel color space converters for JPEG image compression.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2004

An improved synthesis method for low power hardwired FIR filters.

[BibT_eX]

[DOI]

José C. Monteiro

Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

Modeling and designing high performance analog reconfigurable circuits.

[BibT_eX]

[DOI]

Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

ME64 - A Parallel Hardware Architecture for Motion Estimation Implemented in FPGA.

[BibT_eX]

[DOI]

Diogo Zandonai

Marcel Bergerman

Proceedings of the Design Methods and Applications for Distributed Embedded Systems, 2004

Analog Signal Processing Reconfiguration for Systems-on-Chip Using a Fixed Analog Cell Approach.

[BibT_eX]

[DOI]

Proceedings of the Field Programmable Logic and Application, 2004

Throughput and Reconfiguration Time Trade-Offs: From Static to Dynamic Reconfiguration in Dedicated Image Filters.

[BibT_eX]

[DOI]

Marcos R. Boschetti

Proceedings of the Field Programmable Logic and Application, 2004

Design of Very Deep Pipelined Multipliers for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

A Run-Time Reconfigurable Datapath Architecture for Image Processing Applications.

[BibT_eX]

[DOI]

Marcos R. Boschetti

Proceedings of the 2004 Design, 2004

2003

Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths.

[BibT_eX]

[DOI]

José C. Monteiro

Proceedings of the VLSI-SOC: From Systems to Chips, 2003

Applying the GM/ID method in the analysis and design of Miller Amplifier, Comparator and GM-C PASS-B.

[BibT_eX]

Proceedings of the IFIP VLSI-SoC 2003, 2003

ME64 - A Highly Scalable Hardware Parallel Architecture Motion Estimation in FPGA.

[BibT_eX]

[DOI]

Diogo Zandonai

Marcel Bergerman

Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

Analog IC Modules Design Using Trapezoidal Association of MOS Transistors in 0.35µm Technology.

[BibT_eX]

[DOI]

Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

A Universal High-Performance Analog Interface for Signal Processing SOCs.

[BibT_eX]

[DOI]

Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

A New Pipelined Array Architecture for Signed Multiplication.

[BibT_eX]

[DOI]

Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

Complex Branch Profiling for Dynamic Conditional Execution.

[BibT_eX]

[DOI]

Rafael R. dos Santos

Philippe Olivier Alexandre Navaux

Maurício L. Pilla

Mario Nemirovsky

Proceedings of the 15th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2003), 2003

An analog signal interface with constant performance for SoCs.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Exploiting reconfigurability for low-power control of embedded processors.

[BibT_eX]

[DOI]

Edgard de Faria Corrêa

R. Cardozo

Fernando Moraes

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

LIT - An Automatic Layout Generation Tool for Trapezoidal Association of Transistors for Basic Analog Building Blocks.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

2002

Techniques and Mechanisms for Dynamic Reconfiguration in an Image Processor.

[BibT_eX]

[DOI]

Marcos R. Boschetti

Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

Pipelined Entropy Coders for JPEG Compression.

[BibT_eX]

[DOI]

Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

A New Architecture for 2's Complement Gray Encoded Array Multiplier.

[BibT_eX]

[DOI]

Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

A New Architecture for Signed Radix-2m Pure Array Multipliers.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

2001

Design of Functional Blocks for a Speech Recognition Portable System.

[BibT_eX]

[DOI]

José Luis Gómez-Cipriano

Roger Pizzatto Nunes

Dante Barone

Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001

Pipelined Fast 2-D DCT Architecture for JPEG Image Compression.

[BibT_eX]

[DOI]

Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001

Extending Sequencing Graphs for Reconfigurable Applications Modeling.

[BibT_eX]

[DOI]

Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001

Power Efficient Arithmetic Operand Encoding.

[BibT_eX]

[DOI]

Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001

CMOS Mixed-signal Circuits Design on a Digital Array Using Minimum Transistors.

[BibT_eX]

Proceedings of the SOC Design Methodologies, 2001

2000

Specification and design of an Ethernet Interface soft IP.

[BibT_eX]

João Leonardo Fragoso

Eduardo Costa Pereira

Juergen Rochol

Ricardo Reis

J. Braz. Comput. Soc., 2000

Modeling of Short Circuit Power Consumption Using Timing-Only Logic Cell Macromodels.

[BibT_eX]

[DOI]

Fernando Paixão Cortes

Rodrigo Ferrugem Cardoso

Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

A Generator of Trapezoidal Association of Transistors (TAT): Improving Analog Circuits in a Pre-Diffused Transistor Array.

[BibT_eX]

[DOI]

André Luiz Aita

Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

SisECO: Design of an Echo-Canceling IC for Base Band Modems.

[BibT_eX]

[DOI]

Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

Analyzing Instruction Prefetch Schemes in Superscalar Architectures.

[BibT_eX]

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

A frame stream controller IP.

[BibT_eX]

[DOI]

Fernanda Gusmão de Lima

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

TAT transistors on SOT array for mixed analog/digital applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999

Reconfigurable Computing: Viable Applications and Trends.

[BibT_eX]

Proceedings of the VLSI: Systems on a Chip, 1999

OTA Amplifiers Design on Digital Sea-of-Transistors Array.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

Dynamically Reconfigurable Architecture for Image Processor Applications.

[BibT_eX]

[DOI]

Eduardo L. Roehe

Proceedings of the 36th Conference on Design Automation, 1999

1998

Design of CMOS OTA amplifiers and oscillators in a digital sea-of-transistors array.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1994

A Timing Model for VLSI CMOS Circuits Verification and Optimization.

[BibT_eX]

[DOI]

Luís Felipe Uebel

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1990

An experiment on PC-based automated extraction of electrical parameters for VLSI MOSFETs: Methods, algorithms, and implementation.

[BibT_eX]

[DOI]