Judit Freijedo

According to our database1, Judit Freijedo authored at least 16 papers between 2007 and 2013.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2013
Aging monitoring with local sensors in FPGA-based designs.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
Modeling the Effect of Process, Power-Supply Voltage and Temperature Variations on the Timing Response of Nanometer Digital Circuits.
J. Electron. Test., 2012

2011
Lower <i>V</i><sub>DD</sub> Operation of FPGA-Based Digital Circuits Through Delay Modeling and Time Borrowing.
J. Low Power Electron., 2011

Programmable sensor for on-line checking of signal integrity in FPGA-based systems subject to aging effects.
Proceedings of the 12th Latin American Test Workshop, 2011

Modeling the effect of process variations on the timing response of nanometer digital circuits.
Proceedings of the 12th Latin American Test Workshop, 2011

Performance Failure Prediction Using Built-In Delay Sensors in FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

2010
Impact of Power Supply Voltage Variations on FPGA-Based Digital Systems Performance.
J. Low Power Electron., 2010

2009
Measuring clock-signal modulation efficiency for Systems-on-Chip in electromagnetic interference environment.
Proceedings of the 10th Latin American Test Workshop, 2009

Delay-fault tolerance to power supply Voltage disturbances analysis in nanometer technologies.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

2008
Time Management for Low-Power Design of Digital Systems.
J. Low Power Electron., 2008

Delay Modeling for Power Noise and Temperature-Aware Design and Test of Digital Systems.
J. Low Power Electron., 2008

Exploiting Parametric Power Supply and/or Temperature Variations to Improve Fault Tolerance in Digital Circuits.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Robust solution for synchronous communication among multi clock domains.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Enhancing the Tolerance to Power-Supply Instability in Digital Circuits.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous Circuits.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007


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