Marcelino B. Santos

Orcid: 0000-0002-2091-1165

According to our database1, Marcelino B. Santos authored at least 96 papers between 1992 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Paving the Way for the Electronic Design Automation of Power Management Units.
Proceedings of the 19th International Conference on Synthesis, 2023

Delta-Sigma Control Loop For Energy-Efficient Electrical Stimulation with Arbitrary-Shape Stimuli.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023

2022
DRAM Performance Sensor.
Proceedings of the Universal Access in Human-Computer Interaction. Novel Design Approaches and Technologies, 2022

Load Optimized Gate Driving for Charge Pumps.
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022

2021
SRAM Performance Sensor.
Proceedings of the XXXVI Conference on Design of Circuits and Integrated Systems, 2021

2020
Internet of Things and Artificial Intelligence - A Wining Partnership?
Proceedings of the Convergence of Artificial Intelligence and the Internet of Things, 2020

2019
Applying Model Checking in the Verification of a Clock Masking Unit.
Proceedings of the XXXIV Conference on Design of Circuits and Integrated Systems, 2019

2018
Performance Sensor for Reliable Operation.
Proceedings of the Universal Access in Human-Computer Interaction. Virtual, Augmented, and Intelligent Environments, 2018

Low noise, high efficiency, segmented LCD drivers for ultra-low power applications in 22 nm FD-SOI.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

Low-power frequency monitoring circuit for clock failure detection.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

2015
Fault-Tolerance in Field Programmable Gate Array with Dynamic Voltage and Frequency Scaling.
J. Low Power Electron., 2015

Fault-tolerance in FPGA focusing power reduction or performance enhancement.
Proceedings of the 16th Latin-American Test Symposium, 2015

2014
Digital modular control of high frequency DC-DC converters.
Microelectron. J., 2014

Implicit current DC-DC Digital Voltage-Mode Control.
Proceedings of the 23rd IEEE International Symposium on Industrial Electronics, 2014

Performance sensor for tolerance and predictive detection of delay-faults.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

2013
Ultra low power capless LDO with dynamic biasing of derivative feedback.
Microelectron. J., 2013

ActivIC: Design-Based Automatic Characterization of Mixed-Signal Integrated Circuits.
J. Low Power Electron., 2013

Process Variations-Aware Statistical Analysis Framework for Aging Sensors Insertion.
J. Electron. Test., 2013

A self-calibrated 10-bit 1 MSps SAR ADC with reduced-voltage charge-sharing DAC.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Aging monitoring with local sensors in FPGA-based designs.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
Modeling of Inherent Losses of Fully Integrated Switched Capacitor DC-DC Converters.
J. Low Power Electron., 2012

Aging-Aware Power or Frequency Tuning With Predictive Fault Detection.
IEEE Des. Test Comput., 2012

The influence of clock-gating on NBTI-induced delay degradation.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

An ultra-low noise current source for magnetoresistive biosensors biasing.
Proceedings of the 2012 IEEE Biomedical Circuits and Systems Conference, 2012

2011
Smart Control of Internal Supply Voltage Spikes in a Low Voltage DC-DC Buck Converter.
J. Low Power Electron., 2011

On-Line BIST for Performance Failure Prediction Under NBTI-Induced Aging in Safety-Critical Applications.
J. Low Power Electron., 2011

Digital Sliding Mode Control of DC-DC Buck Converters.
J. Low Power Electron., 2011

Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensors.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

On-line BIST for performance failure prediction under aging effects in automotive safety-critical applications.
Proceedings of the 12th Latin American Test Workshop, 2011

ICT: Interface software for the characterization and test of mixed-signal power cores.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Analysis of a monolithic buck converter's pMOS switch during turn off.
Proceedings of EUROCON 2011, 2011

Digital LQR control with Kalman Estimator for DC-DC Buck converter.
Proceedings of EUROCON 2011, 2011

Mixed-Signal Fault Equivalence: Search and Evaluation.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
Low-sensitivity to process variations aging sensor for automotive safety-critical applications.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Predictive error detection by on-line aging monitoring.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Programmable aging sensor for automotive safety-critical applications.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Noise Minimization for Low Power Bandgap Reference and Low Dropout Regulator Cores.
J. Low Power Electron., 2009

Gate Driver Voltage Optimization for Multi-Mode Low Power DC-DC Conversion.
J. Low Power Electron., 2009

Measuring clock-signal modulation efficiency for Systems-on-Chip in electromagnetic interference environment.
Proceedings of the 10th Latin American Test Workshop, 2009

Built-in aging monitoring for safety-critical applications.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Delay-fault tolerance to power supply Voltage disturbances analysis in nanometer technologies.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Controllability and observability in mixed signal cores.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

2008
Level Shifters and DCVSL for a Low-Voltage CMOS 4.2-V Buck Converter.
IEEE Trans. Ind. Electron., 2008

Time Management for Low-Power Design of Digital Systems.
J. Low Power Electron., 2008

Signal Integrity Enhancement in Digital Circuits.
IEEE Des. Test Comput., 2008

Monolithic Multi-mode DC-DC Converter with Gate Voltage Optimization.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Exploiting Parametric Power Supply and/or Temperature Variations to Improve Fault Tolerance in Digital Circuits.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Adjustable low consumption circuit for monitorization of power source voltages in a SoC.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Functional-oriented mask-based built-in self-test.
IET Comput. Digit. Tech., 2007

Enhancing the Tolerance to Power-Supply Instability in Digital Circuits.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous Circuits.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006
BIST Architectures and Fault Emulation.
Proceedings of the 7th Latin American Test Workshop, 2006

DFT and Probabilistic Testability Analysis at RTL.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

Functional-Oriented BIST of Sequential Circuits Aiming at Dynamic Faults Coverage.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

Probabilistic Testability Analysis and DFT Methods at RTL.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

2005
Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip.
J. Electron. Test., 2005

Dynamic Fault Test and Diagnosis in Digital Systems Using Multiple Clock Schemes and Multi-VDD Test.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

2004
On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level.
J. Electron. Test., 2004

Built-In Self-Test Quality Assessment Using Hardware Fault Emulation In FPGAs.
Comput. Artif. Intell., 2004

Modeling and Simulation of Time Domain Faults in Digital Systems.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

FPGAs BIST Evaluation.
Proceedings of the Field Programmable Logic and Application, 2004

A Probabilistic Method for the Computation of Testability of RTL Constructs.
Proceedings of the 2004 Design, 2004

2003
Property Coverage for Quality Assessment of Fault Tolerant or Fail Safe Systems.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Fault Simulation Using Partially Reconfigurable Hardware.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

RTL Test Pattern Generation for High Quality Loosely Deterministic BIST.
Proceedings of the 2003 Design, 2003

2002
RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage.
J. Electron. Test., 2002

Design and Test of a Certifiable ASIC for a Safety-Critical Gas Burner Control System.
J. Electron. Test., 2002

On High-Quality, Low Energy BIST Preparation at RT-Level.
Proceedings of the 3rd Latin American Test Workshop, 2002

RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Self-Checking and Fault Tolerance Quality Assessment Using Fault Sampling.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2001
RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems.
J. Electron. Test., 2001

Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-level.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Design and Test of Certifiable ASICs for Safety-Critical Gas Burners Contro.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

2000
Low Power BIST by Filtering Non-Detecting Vectors.
J. Electron. Test., 2000

Experiments on RTL ATPG and Fault Simulation for High Defect Coverage in Digital Systems-on-a-Chip.
Proceedings of the 1st Latin American Test Workshop, 2000

Quality of Electronic Design: From Architectural Level to Test Coverage.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

RTL-based functional test generation for high defects coverage in digital SOCs.
Proceedings of the 5th European Test Workshop, 2000

1999
Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

From system level to defect-oriented test: a case study.
Proceedings of the 4th European Test Workshop, 1999

Defect-Oriented Mixed-Level Fault Simulation of Digital Systems-on-a-Chip Using HDL.
Proceedings of the 1999 Design, 1999

1998
Defect-oriented test quality assessment using fault sampling and simulation.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Defect-oriented testing of analogue and mixed signal ICs.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1996
Defect-Oriented IC Test and Diagnosis Using VHDL Fault Simulation.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

VHDL fault simulation for defect-oriented test and diagnosis of digital ICs.
Proceedings of the conference on European design automation, 1996

1995
Test preparation for high coverage of physical defects in CMOS digital ICs.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Test preparation methodology for high coverage of physical defects in CMOS digital ICs.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
Back Annotation of Physical Defects into Gate-Level, Realistic Faults in Digital ICs.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

On the Analysis of Routing Cells and Adjacency Faults in CMOS Digital Circuits.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

1993
Realistic Fault Analysis of CMOS Analog Building Blocks.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

Experiments on Bridging Fault Analysis and Layout-Level DFT for CMOS Designs.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

1992
On the design of a highly testable cell library.
Microprocess. Microprogramming, 1992

Physical DFT for High Coverage of Realistic Faults.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992


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