Fabian Vargas
Affiliations:- Pontifical Catholic University of Rio Grande do Sul, Porto Alegre, Brazil
According to our database1,
Fabian Vargas
authored at least 122 papers
between 1993 and 2023.
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Bibliography
2023
Artificial Neural Network Accelerator for Classification of In-Field Conducted Noise in Integrated Circuits' DC Power Lines.
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023
2022
Failure Probability due to Radiation-induced Effects in FinFET SRAM Cells under Process Variations.
Proceedings of the 23rd IEEE Latin American Test Symposium, 2022
2021
Analysis and Detection of Open-gate Defects in Redundant Structures of a FinFET SRAM Cell.
J. Electron. Test., 2021
Proceedings of the 22nd IEEE Latin American Test Symposium, 2021
2020
PCoSA: A product error correction code for use in memory devices targeting space applications.
Integr., 2020
Analysis and detection of hard-to-detect full open defects in FinFET based SRAM cells.
Proceedings of the IEEE Latin-American Test Symposium, 2020
Run-time Hardware Reconfiguration of Functional Units to Support Mixed-Critical Applications.
Proceedings of the IEEE Latin-American Test Symposium, 2020
2019
J. Electron. Test., 2019
Proceedings of the IEEE Latin American Test Symposium, 2019
A New Approach to Guarantee Critical Task Schedulability in TDMA-Based Bus Access of Multicore Architecture.
Proceedings of the IEEE Latin American Test Symposium, 2019
2018
A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs.
Microelectron. Reliab., 2018
Microelectron. Reliab., 2018
J. Electron. Test., 2018
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018
2017
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017
Proceedings of the 18th IEEE Latin American Test Symposium, 2017
Proceedings of the 18th IEEE Latin American Test Symposium, 2017
2016
Effectiveness of a hardware-based approach to detect resistive-open defects in SRAM cells under process variations.
Microelectron. Reliab., 2016
J. Electron. Test., 2016
NBTI-Aware Design of Integrated Circuits: A Hardware-Based Approach for Increasing Circuits' Life Time.
J. Electron. Test., 2016
Experimental assessment of using network coding and cooperative diversity techniques in IEEE 802.15.4 wireless sensor networks.
Proceedings of the IEEE World Conference on Factory Communication Systems, 2016
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Proceedings of the 17th Latin-American Test Symposium, 2016
Proceedings of the 17th Latin-American Test Symposium, 2016
Proceedings of the 13th IEEE International Conference on Networking, Sensing, and Control, 2016
2015
Microelectron. Reliab., 2015
An early prediction methodology for aging sensor insertion to assure safe circuit operation due to NBTI aging.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015
Proceedings of the 28th International Conference on VLSI Design, 2015
Proceedings of the 16th Latin-American Test Symposium, 2015
Proceedings of the 16th Latin-American Test Symposium, 2015
Proceedings of the 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits, 2015
SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015
2014
A Primer on Energy-Efficient Synchronization of WSN Nodes over Correlated Rayleigh Fading Channels.
IEEE Wirel. Commun. Lett., 2014
Proceedings of the 15th Latin American Test Workshop, 2014
A novel control strategy for fail-safe cyclic data exchange in wireless sensor networks.
Proceedings of the 15th Latin American Test Workshop, 2014
2013
Technique based on On-Chip Current Sensors and Neighbourhood Comparison Logic to detect resistive-open defects in SRAMs.
Proceedings of the 14th Latin American Test Workshop, 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
Reliability analysis of an on-chip watchdog for embedded systems exposed to radiation and EMI.
Proceedings of the 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
2012
Evaluating the Effectiveness of a Software-Based Technique Under SEEs Using FPGA-Based Fault Injection Approach.
J. Electron. Test., 2012
Modeling the Effect of Process, Power-Supply Voltage and Temperature Variations on the Timing Response of Nanometer Digital Circuits.
J. Electron. Test., 2012
J. Electron. Test., 2012
Proceedings of the 13th Latin American Test Workshop, 2012
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012
2011
Reliability Analysis of H-Tree Random Access Memories Implemented With Built in Current Sensors and Parity Codes for Multiple Bit Upset Correction.
IEEE Trans. Reliab., 2011
Lower <i>V</i><sub>DD</sub> Operation of FPGA-Based Digital Circuits Through Delay Modeling and Time Borrowing.
J. Low Power Electron., 2011
12th "IEEE Latin-American Test Workshop" Porto de Galinhas, Brazil, 27-30 March 2011.
J. Low Power Electron., 2011
Programmable sensor for on-line checking of signal integrity in FPGA-based systems subject to aging effects.
Proceedings of the 12th Latin American Test Workshop, 2011
Using an FPGA-based fault injection technique to evaluate software robustness under SEEs: A case study.
Proceedings of the 12th Latin American Test Workshop, 2011
Proceedings of the 12th Latin American Test Workshop, 2011
Proceedings of the 12th Latin American Test Workshop, 2011
Modeling the effect of process variations on the timing response of nanometer digital circuits.
Proceedings of the 12th Latin American Test Workshop, 2011
Configurable platform for IC combined tests of total-ionizing dose radiation and electromagnetic immunity.
Proceedings of the 12th Latin American Test Workshop, 2011
An intellectual property core to detect task schedulling-related faults in RTOS-based embedded systems.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
Proceedings of the 16th European Test Symposium, 2011
2010
J. Low Power Electron., 2010
Proceedings of the 11th Latin American Test Workshop, 2010
Proceedings of the 11th Latin American Test Workshop, 2010
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
Evaluating a Transmission Power Self-Optimization Technique for WSN in EMI Environments.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010
2009
Measuring clock-signal modulation efficiency for Systems-on-Chip in electromagnetic interference environment.
Proceedings of the 10th Latin American Test Workshop, 2009
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Delay-fault tolerance to power supply Voltage disturbances analysis in nanometer technologies.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
2008
J. Low Power Electron., 2008
Delay Modeling for Power Noise and Temperature-Aware Design and Test of Digital Systems.
J. Low Power Electron., 2008
Exploiting Parametric Power Supply and/or Temperature Variations to Improve Fault Tolerance in Digital Circuits.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008
2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007
2006
IEEE Trans. Computers, 2006
Using Multiple Clock Schemes and Multi-Temperature Test for Dynamic Fault Detection in Digital Systems.
Proceedings of the 7th Latin American Test Workshop, 2006
Observing SRAM-based FPGA Robustness in EMI-exposed Environments.
Proceedings of the 7th Latin American Test Workshop, 2006
Dynamic Fault Detection in Digital Systems Using Dynamic Voltage Scaling and Multi-Temperature Schemes.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
Summarizing a time-sensitive control-flow checking monitoring for multitask systems-on-chip.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006
2005
Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip.
J. Electron. Test., 2005
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
Dynamic Fault Test and Diagnosis in Digital Systems Using Multiple Clock Schemes and Multi-VDD Test.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core.
Proceedings of the 2005 International Conference on Dependable Systems and Networks (DSN 2005), 28 June, 2005
2004
Merging a DSP-Oriented Signal Integrity Technique and SW-Based Fault Handling Mechanisms to Ensure Reliable DSP Systems.
J. Electron. Test., 2004
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004
2003
J. Electron. Test., 2003
Introducing SW-Based Fault Handling Mechanisms to Cope with EMI in Embedded Electronics: Are They A Good Remedy?
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003
2002
Electrocardiogram Pattern Recognition by Means of MLP Network and PCA: A Case Study on Equal Amount of Input Signal Types.
Proceedings of the 7th Brazilian Symposium on Neural Networks (SBRN 2002), 2002
A New Learning Approach to Design Fault Tolerant ANNs: Finally a Zero HW-SW Overhead.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002
Experimental Results of a Recovery Block Scheme to Handle Noise in Speech Recognition Systems.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002
2001
Improving Reconfigurable Systems Reliability by Combining Periodical Test and Redundancy Techniques: A Case Study.
J. Electron. Test., 2001
Summarizing a New Approach to Design Speech Recognition Systems: A Reliable Noise-Immune HW-SW Version.
Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001
Orienting Redundancy and HW/SW Codesign Techniques Towards Speech Recognition Systems.
Proceedings of the 2nd Latin American Test Workshop, 2001
Circuit Modeling and Fault Injection Approach to Predict SEU Rate and MTTF in Complex Circuits.
Proceedings of the 2nd Latin American Test Workshop, 2001
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001
Proceedings of the IEEE International Conference on Acoustics, 2001
2000
Recent Improvements on the Specification of Transient-Fault Tolerant VHDL Descriptions: A Case-Study for Area Overhead Analysis.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000
Fault-Tolerance in VHDL Description: Transient-Fault Injection & Early Reliability Estimation.
Proceedings of the 1st Latin American Test Workshop, 2000
Merging BIST and Configurable Computing Technology to Improve Availability in Space Applications.
Proceedings of the 1st Latin American Test Workshop, 2000
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000
1998
Reliability Verification of Fault-Tolerant Systems Design based on Mutation Analysis.
Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998
1995
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995
1993
Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993