Jun Ho Bahn

According to our database, Jun Ho Bahn authored at least 14 papers between 2007 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2012

Parallel low-density parity check decoding on a network-on-chip-based multiprocessor platform.

W.-H. Hu, C.-Y. Chen, Jun Ho Bahn, Nader Bagherzadeh

IET Comput. Digit. Tech., 2012

2010

Parallel processing for block ciphers on a fault tolerant networked processor array.

Yoon Seok Yang, Jun Ho Bahn, Seung Eun Lee, Jungsook Yang, Nader Bagherzadeh

Int. J. High Perform. Syst. Archit., 2010

2009

Parallel FFT Algorithms on Network-on-Chips.

Jun Ho Bahn, Jungsook Yang, Wen-Hsiang Hu, Nader Bagherzadeh

J. Circuits Syst. Comput., 2009

Parallel LDPC Decoding on a Network-on-Chip Based Multiprocessor Platform.

Wen-Hsiang Hu, Jun Ho Bahn, Nader Bagherzadeh

Proceedings of the 21st International Symposium on Computer Architecture and High Performance Computing, 2009

Parallel and Pipeline Processing for Block Cipher Algorithms on a Network-on-Chip.

Yoon Seok Yang, Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh

Proceedings of the Sixth International Conference on Information Technology: New Generations, 2009

2008

On Design and Application Mapping of a Network-on-Chip(NoC) Architecture.

Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungsook Yang, Nader Bagherzadeh

Parallel Process. Lett., 2008

Design of simulation and analytical models for a 2D-meshed asymmetric adaptive router.

Jun Ho Bahn, Nader Bagherzadeh

IET Comput. Digit. Tech., 2008

Parallel FFT Algorithms on Network-on-Chips.

Jun Ho Bahn, Jungsook Yang, Nader Bagherzadeh

Proceedings of the Fifth International Conference on Information Technology: New Generations (ITNG 2008), 2008

Self-optimized Routing in a Network on-a-Chip.

Wolfgang Trumler, Sebastian Schlingmann, Theo Ungerer, Jun Ho Bahn, Nader Bagherzadeh

Proceedings of the Biologically-Inspired Collaborative Computing, 2008

Efficient Parallel Buffer Structure and Its Management Scheme for a Robust Network-on-Chip (NoC) Architecture.

Jun Ho Bahn, Nader Bagherzadeh

Proceedings of the Advances in Computer Science and Engineering, 2008

A Generic Network Interface Architecture for a Networked Processor Array (NePA).

Seung Eun Lee, Jun Ho Bahn, Yoon Seok Yang, Nader Bagherzadeh

Proceedings of the Architecture of Computing Systems, 2008

2007

Design of a router for network-on-chip.

Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh

Int. J. High Perform. Syst. Archit., 2007

Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP).

Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh

Proceedings of the 19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 2007

On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture.

Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh

Proceedings of the Fourth International Conference on Information Technology: New Generations (ITNG 2007), 2007