Nader Bagherzadeh
Orcid: 0000-0001-7216-0546Affiliations:
- University of California Irvine, CA, USA
- University of Texas at Austin, TX, USA (PhD 1987)
According to our database1,
Nader Bagherzadeh
authored at least 273 papers
between 1985 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2014, "For contributions to the design and analysis of coarse-grained reconfigurable processor architectures".
Timeline
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Bibliography
2024
ARMAN: A Reconfigurable Monolithic 3D Accelerator Architecture for Convolutional Neural Networks.
CoRR, 2024
2023
Efficient realization of quantum balanced ternary reversible multiplier building blocks: A great step towards sustainable computing.
Sustain. Comput. Informatics Syst., December, 2023
IEEE Trans. Emerg. Top. Comput., 2023
CoRR, 2023
2022
Guest Editorial: Thematic Section on Applications of Emerging Computing Technologies in Smart Manufacturing and Industry 4.0.
IEEE Trans. Emerg. Top. Comput., 2022
IEEE Trans. Emerg. Top. Comput., 2022
IEEE Trans. Emerg. Top. Comput., 2022
IEEE Trans. Emerg. Top. Comput., 2022
A storage-efficient ensemble classification using filter sharing on binarized convolutional neural networks.
PeerJ Comput. Sci., 2022
Proceedings of the IEEE International Conference on Industrial Technology, 2022
2021
IEEE Trans. Emerg. Top. Comput., 2021
Enhancing Reliability of Emerging Memory Technology for Machine Learning Accelerators.
IEEE Trans. Emerg. Top. Comput., 2021
CoRR, 2021
Comput. Biol. Medicine, 2021
Proceedings of the 29th Euromicro International Conference on Parallel, 2021
2020
Adaptive HTF-MPR: An Adaptive Heterogeneous TensorFlow Mapper Utilizing Bayesian Optimization and Genetic Algorithms.
ACM Trans. Intell. Syst. Technol., 2020
IRHT: An SDC detection and recovery architecture based on value locality of instruction binary codes.
Microprocess. Microsystems, 2020
J. Parallel Distributed Comput., 2020
Divisible load scheduling of image processing applications on the heterogeneous star and tree networks using a new genetic algorithm.
Concurr. Comput. Pract. Exp., 2020
Comput. Electr. Eng., 2020
A novel digital fuzzy system for image edge detection based on wrap-gate carbon nanotube transistors.
Comput. Electr. Eng., 2020
Comput. Biol. Medicine, 2020
Proceedings of the 28th Euromicro International Conference on Parallel, 2020
Proceedings of the 28th Euromicro International Conference on Parallel, 2020
Supervised Machine-Learning Algorithms in Real-time Prediction of Hypotensive Events.
Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020
2019
IEEE Trans. Computers, 2019
Toward efficient implementation of basic balanced ternary arithmetic operations in CNFET technology.
Microelectron. J., 2019
CLBM: Controlled load-balancing mechanism for congestion management in silicon interposer NoC architecture.
J. Syst. Archit., 2019
A new approach to the Population-Based Incremental Learning algorithm using virtual regions for task mapping on NoCs.
J. Syst. Archit., 2019
Computational storage: an efficient and scalable platform for big data and HPC applications.
J. Big Data, 2019
DICA: destination intensity and congestion-aware output selection strategy for network-on-chip systems.
IET Comput. Digit. Tech., 2019
Novel CNFET ternary circuit techniques for high-performance and energy-efficient design.
IET Circuits Devices Syst., 2019
CoRR, 2019
Proceedings of the 27th Euromicro International Conference on Parallel, 2019
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the 21st IEEE International Conference on High Performance Computing and Communications; 17th IEEE International Conference on Smart City; 5th IEEE International Conference on Data Science and Systems, 2019
Proceedings of the 27th European Symposium on Artificial Neural Networks, 2019
Proceedings of the 3rd IEEE International Conference on Edge Computing, 2019
Power and Performance Optimal NoC Design for CPU-GPU Architecture Using Formal Models.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
A Cost-Efficient Iterative Truncated Logarithmic Multiplication for Convolutional Neural Networks.
Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019
2018
AROMa: Aging-Aware Deadlock-Free Adaptive Routing Algorithm and Online Monitoring in 3D NoCs.
IEEE Trans. Parallel Distributed Syst., 2018
IEEE Trans. Fuzzy Syst., 2018
Design and Evaluation of a Spintronic In-Memory Processing Platform for Nonvolatile Data Encryption.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IEEE Trans. Computers, 2018
LEAD: An Adaptive 3D-NoC Routing Algorithm with Queuing-Theory Based Analytical Verification.
IEEE Trans. Computers, 2018
STABLE: Stress-Aware Boolean Matching to Mitigate BTI-Induced SNM Reduction in SRAM-Based FPGAs.
IEEE Trans. Computers, 2018
First-Last: A Cost-Effective Adaptive Routing Solution for TSV-Based Three-Dimensional Networks-on-Chip.
IEEE Trans. Computers, 2018
Energy and performance-aware application mapping for inhomogeneous 3D networks-on-chip.
J. Syst. Archit., 2018
Design and Power Analysis of New Coplanar One-Bit Full-Adder Cell in Quantum-Dot Cellular Automata.
J. Low Power Electron., 2018
ACM J. Emerg. Technol. Comput. Syst., 2018
Hospital enterprise Architecture Framework (Study of Iranian University Hospital Organization).
Int. J. Medical Informatics, 2018
IET Comput. Digit. Tech., 2018
Comput. Electr. Eng., 2018
Proceedings of the 26th Euromicro International Conference on Parallel, 2018
Divisible Load Scheduling of Image Processing Applications on the Heterogeneous Star Network Using a new Genetic Algorithm.
Proceedings of the 26th Euromicro International Conference on Parallel, 2018
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018
HTF-MPR: A heterogeneous TensorFlow mapper targeting performance using genetic algorithms and gradient boosting regressors.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Low-power implementation of Mitchell's approximate logarithmic multiplication for convolutional neural networks.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
IEEE Trans. Computers, 2017
IEEE Trans. Computers, 2017
IEEE Trans. Computers, 2017
A Single Parity-Check Digit for One Trit Error Detection in Ternary Communication Systems: Gate-Level and Transistor-Level Designs.
J. Multiple Valued Log. Soft Comput., 2017
Microprocess. Microsystems, 2017
J. Low Power Electron., 2017
IET Circuits Devices Syst., 2017
A new approach for designing compressors with a new hardware-friendly mathematical method for multi-input XOR gates.
IET Circuits Devices Syst., 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Performance and Energy Aware Inhomogeneous 3D Networks-on-Chip Architecture Generation.
IEEE Trans. Parallel Distributed Syst., 2016
IEEE Trans. Computers, 2016
Loss-Aware Switch Design and Non-Blocking Detection Algorithm for Intra-Chip Scale Photonic Interconnection Networks.
IEEE Trans. Computers, 2016
A Resilient Routing Algorithm with Formal Reliability Analysis for Partially Connected 3D-NoCs.
IEEE Trans. Computers, 2016
Microelectron. J., 2016
J. Low Power Electron., 2016
Comput. Electr. Eng., 2016
Comput. Electr. Eng., 2016
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016
ADVOCAT: Automated deadlock verification for on-chip cache coherence and interconnects.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Computers, 2015
Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach.
Microelectron. J., 2015
Microprocess. Microsystems, 2015
J. Low Power Electron., 2015
ACM J. Emerg. Technol. Comput. Syst., 2015
Design and Verification of New n-Bit Quantum-Dot Synchronous Counters Using Majority Function-Based JK Flip-Flops.
J. Circuits Syst. Comput., 2015
Integr., 2015
Voltage mirror circuit by carbon nanotube field effect transistors for mirroring dynamic random access memories in multiple-valued logic and fuzzy logic.
IET Circuits Devices Syst., 2015
Computing, 2015
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015
An Adaptive, Low Restrictive and Fault Resilient Routing Algorithm for 3D Network-on-Chip.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015
2014
ACM Trans. Embed. Comput. Syst., 2014
Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Network-on-Chip.
Microprocess. Microsystems, 2014
Novel Robust Single Layer Wire Crossing Approach for Exclusive OR Sum of Products Logic Design with Quantum-Dot Cellular Automata.
J. Low Power Electron., 2014
Comput. Electr. Eng., 2014
Proceedings of the 2nd International Workshop on Many-core Embedded Systems, 2014
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
2013
From UML specifications to mapping and scheduling of tasks into a NoC, with reliability considerations.
J. Syst. Archit., 2013
J. Comput. Syst. Sci., 2013
J. Comput. Syst. Sci., 2013
IET Comput. Digit. Tech., 2013
Quality of Service Optimization for Network-on-Chip Using Bandwidth-Constraint Mapping Algorithm.
Proceedings of the 21st Euromicro International Conference on Parallel, 2013
Proceedings of the 21st Euromicro International Conference on Parallel, 2013
Proceedings of the Network on Chip Architectures, 2013
2012
A software pipelining algorithm of streaming applications with low buffer requirements.
Sci. Iran., 2012
A load-balanced congestion-aware wireless network-on-chip design for multi-core platforms.
Microprocess. Microsystems, 2012
Microprocess. Microsystems, 2012
Mapping and Scheduling in Heterogeneous NoC through Population-Based Incremental Learning.
J. Univers. Comput. Sci., 2012
High-throughput differentiated service provision router architecture for wireless network-on-chip.
Int. J. High Perform. Syst. Archit., 2012
Parallel low-density parity check decoding on a network-on-chip-based multiprocessor platform.
IET Comput. Digit. Tech., 2012
IET Comput. Digit. Tech., 2012
A formally verified deadlock-free routing function in a fault-tolerant NoC architecture.
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012
Proceedings of the 20th Euromicro International Conference on Parallel, 2012
2011
J. Syst. Archit., 2011
A scheduling approach for distributed resource architectures with scarce communication resources.
Int. J. High Perform. Syst. Archit., 2011
Load Balancing for Data-Parallel Applications on Network-on-Chip Enabled Multi-processor Platform.
Proceedings of the 19th International Euromicro Conference on Parallel, 2011
Proceedings of the 19th International Euromicro Conference on Parallel, 2011
2010
Int. J. High Perform. Syst. Archit., 2010
Proceedings of the 18th Euromicro Conference on Parallel, 2010
Proceedings of the 17th International Conference on Telecommunications, 2010
Proceedings of the 39th International Conference on Parallel Processing, 2010
2009
A framework for low energy data management in reconfigurable multi-context architectures.
J. Syst. Archit., 2009
J. Circuits Syst. Comput., 2009
Optimisations for LocSens - an indoor location tracking system using wireless sensors.
Int. J. Sens. Networks, 2009
Comput. Electr. Eng., 2009
Resource management and task partitioning and scheduling on a run-time reconfigurable embedded system.
Comput. Electr. Eng., 2009
Proceedings of the 21st International Symposium on Computer Architecture and High Performance Computing, 2009
Proceedings of the Sixth International Conference on Information Technology: New Generations, 2009
Proceedings of the Sixth International Conference on Information Technology: New Generations, 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Mobile Agents for Wireless Sensor Networks.
Proceedings of the 2009 International Conference on Wireless Networks, 2009
2008
Parallel Process. Lett., 2008
An ASIC design and formal analysis of a novel pipelined and parallel sorting accelerator.
Integr., 2008
Scheduling methodology for conditional execution of kernels onto multicontext reconfigurable architectures.
IET Comput. Digit. Tech., 2008
Design of simulation and analytical models for a 2D-meshed asymmetric adaptive router.
IET Comput. Digit. Tech., 2008
RECFEC: A Reconfigurable FEC Processor for Viterbi, Turbo, Reed-Solomon and LDPC Coding.
Proceedings of the WCNC 2008, IEEE Wireless Communications & Networking Conference, March 31 2008, 2008
Proceedings of the Fifth International Conference on Information Technology: New Generations (ITNG 2008), 2008
Proceedings of the Biologically-Inspired Collaborative Computing, 2008
ESTR - Energy Saving Token Ring Protocol for Wireless Sensor Networks.
Proceedings of the 2008 International Conference on Wireless Networks, 2008
Proceedings of the 17th International Conference on Computer Communications and Networks, 2008
Efficient Parallel Buffer Structure and Its Management Scheme for a Robust Network-on-Chip (NoC) Architecture.
Proceedings of the Advances in Computer Science and Engineering, 2008
Specific Absorption Rate Calculation using Parallel 3D Finite Difference Time Domain Technique.
Proceedings of the 2008 International Conference on Communications in Computing, 2008
Proceedings of the Architecture of Computing Systems, 2008
2007
Ultra-fast and efficient algorithm for energy optimization by gradient-based stochastic voltage and task scheduling.
ACM Trans. Design Autom. Electr. Syst., 2007
Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP).
Proceedings of the 19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 2007
Proceedings of the Fourth International Conference on Information Technology: New Generations (ITNG 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007
Configuration and Data Scheduling for Executing Dynamic Applications onto Multi-Context Reconfigurable Architectures.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007
Integrating Power Management into Distributed Real-time Systems at Very Low Implementation Cost.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
Proceedings of the Architecture of Computing Systems, 2007
2006
A Multi-Standard Viterbi Decoder for Mobile Applications Using a Reconfigurable Architecture.
Proceedings of the 64th IEEE Vehicular Technology Conference, 2006
Proceedings of the Third International Conference on Information Technology: New Generations (ITNG 2006), 2006
Configuration Scheduling for Conditional Branch Execution Onto Multi-Context Reconfigurable Architectures.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006
Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys).
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006
2005
Low Power Data Prefetch for 3D Image Applications on Coarse-Grain Reconfigurable Architectures.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
An Approach to Execute Conditional Branches onto SIMD Multi-Context Reconfigurable Architectures.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005
2004
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004
An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
Efficient mapping of hierarchical trees on coarse-grain reconfigurable architectures.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004
Proceedings of the First Conference on Computing Frontiers, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
ACM Trans. Embed. Comput. Syst., 2003
Algorithm optimizations and mapping scheme for interactive ray tracing on a reconfigurable architecture.
Comput. Graph., 2003
Proceedings of the 15th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2003), 2003
Proceedings of the 2003 International Conference on Image Processing, 2003
Proceedings of the 24th Annual Conference of the European Association for Computer Graphics, 2003
A Component Oriented Simulator for HW/SW Co-Designs.
Proceedings of the First Workshop on Embedded Systems for Real-Time Multimedia, 2003
Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures.
Proceedings of the 2003 Design, 2003
Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver.
Proceedings of the 2003 Design, 2003
Proceedings of the 2003 Design, 2003
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Proceedings of the Embedded Software for SoC, 2003
2002
Des. Autom. Embed. Syst., 2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002
Proceedings of the 14th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2002), 2002
Power-Aware Task Motion for Enhancing Dynamic Range of Embedded Systems with Renewable Energy Sources.
Proceedings of the Power-Aware Computer Systems, Second International Workshop, 2002
Proceedings of the 2002 International Symposium on Information Technology (ITCC 2002), 2002
Combined Functional Partitioning and Communication Speed Selection for Networked Voltage-Scalable Processors.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002
MorphoSys: A Coarse Grain Reconfigurable Architecture for Multimedia Applications (Research Note).
Proceedings of the Euro-Par 2002, 2002
Proceedings of the Euro-Par 2002, 2002
Improving the Operation Autonomy of SIMD Processing Elements by Using Guarded Instructions and Pseudo Branches.
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002
Proceedings of the 2002 Design, 2002
Communication speed selection for embedded systems with networked voltage-scalable processors.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002
2001
IEEE Trans. Very Large Scale Integr. Syst., 2001
A formal approach to context scheduling for multicontext reconfigurable architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2001
Kernel scheduling techniques for efficient solution space exploration in reconfigurable computing.
J. Syst. Archit., 2001
Proceedings of the IEEE International Conference on Systems, 2001
Proceedings of the 14th International Symposium on Systems Synthesis, 2001
Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems.
Proceedings of the 38th Design Automation Conference, 2001
A constraint-based application model and scheduling techniques for power-aware systems.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001
A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture.
Proceedings of the 2001 International Conference on Compilers, 2001
2000
J. VLSI Signal Process., 2000
<i>MorphoSys</i>: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications.
IEEE Trans. Computers, 2000
Guest Editors' Introduction: Configurable Computing.
IEEE Des. Test Comput., 2000
Configuration Management in Multi-Context Reconfigurable Systems for Simultaneous Performance and Power Optimization.
Proceedings of the 13th International Symposium on System Synthesis, 2000
Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000
MorphoSys: case study of a reconfigurable computing system targeting multimedia applications.
Proceedings of the 37th Conference on Design Automation, 2000
1999
Proceedings of the 12th International Symposium on System Synthesis, 1999
MorphoSys: A Reconfigurable Processor Trageted to High Performance Image Application.
Proceedings of the Parallel and Distributed Processing, 1999
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999
Proceedings of the 1st NASA / DoD Workshop on Evolvable Hardware (EH '99), 1999
1998
Modeled and Measured Instruction Fetching Performance for Superscalar Microprocessors.
IEEE Trans. Parallel Distributed Syst., 1998
Low Expansion Packings and Embeddings of Hypercubes into Star Graphs: A Performance-Oriented Approach.
IEEE Trans. Parallel Distributed Syst., 1998
Pattern Recognit. Lett., 1998
Microprocess. Microsystems, 1998
Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998
1997
Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), 1997
1996
Inf. Process. Lett., 1996
Average distance and routing algorithms in the star-connected cycles interconnection network.
Proceedings of the Eighth IEEE Symposium on Parallel and Distributed Processing, 1996
Hamiltonicity of the Clustered-Star Graph with Embedding Applications.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1996
Proceedings of the Second International Symposium on High-Performance Computer Architecture, 1996
Proceedings of the Euro-Par '96 Parallel Processing, 1996
Variable-Dilation Embeddings of Hypercubes into Star Graphs: Performance Metrics, Mapping Functions, and Routing.
Proceedings of the Euro-Par '96 Parallel Processing, 1996
Proceedings of the Fifth International Conference on Parallel Architectures and Compilation Techniques, 1996
Proceedings of the Fifth International Conference on Parallel Architectures and Compilation Techniques, 1996
1995
IEEE Trans. Parallel Distributed Syst., 1995
J. Parallel Distributed Comput., 1995
Design and implementation of a 100 MHz centralized instruction window for a superscalar microprocessor.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995
Proceedings of the 28th Annual Hawaii International Conference on System Sciences (HICSS-28), 1995
1994
IEEE Trans. Parallel Distributed Syst., 1994
IEEE Trans. Parallel Distributed Syst., 1994
A performance comparison of several superscalar processor models with a VLIW processor.
Microprocess. Microsystems, 1994
J. Parallel Distributed Comput., 1994
Int. J. Pattern Recognit. Artif. Intell., 1994
1993
IEEE Trans. Computers, 1993
Proceedings of the Seventh International Parallel Processing Symposium, 1993
Proceedings of the 1993 International Conference on Parallel Processing, 1993
1992
Pattern Recognit. Lett., 1992
Microprocess. Microsystems, 1992
Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992
Proceedings of the 6th International Parallel Processing Symposium, 1992
On Design and Performance Analysis of a Superscalar Architecture.
Proceedings of the 1992 International Conference on Parallel Processing, 1992
Proceedings of the Digest of Papers: FTCS-22, 1992
1991
IEEE Trans. Knowl. Data Eng., 1991
Proceedings of the Fifth International Parallel Processing Symposium, Proceedings, Anaheim, California, USA, April 30, 1991
Hypermesh: A Combined Quad Tree and Mesh Network for Parallel Processing.
Proceedings of the International Conference on Parallel Processing, 1991
Parallel Hough Transform for Image Processing on a Pyramid Architecture.
Proceedings of the International Conference on Parallel Processing, 1991
A Percolation Based VLIW Architecture.
Proceedings of the International Conference on Parallel Processing, 1991
1990
Int. J. Parallel Program., 1990
1987
Int. J. Parallel Program., 1987
Proceedings of the 1987 Symposium on the Simulation of Computer Networks, 1987
1986
1985
Network Facility for a Reconfigurable Computer Architecture.
Proceedings of the 5th International Conference on Distributed Computing Systems, 1985