Nader Bagherzadeh

According to our database1, Nader Bagherzadeh authored at least 256 papers between 1985 and 2021.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2014, "For contributions to the design and analysis of coarse-grained reconfigurable processor architectures".

Timeline

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Bibliography

2021
PLAM: a Posit Logarithm-Approximate Multiplier for Power Efficient Posit-based DNNs.
CoRR, 2021

Predicting hypotension in the ICU using noninvasive physiological signals.
Comput. Biol. Medicine, 2021

Application Characterization for Near Memory Processing.
Proceedings of the 29th Euromicro International Conference on Parallel, 2021

2020
Adaptive HTF-MPR: An Adaptive Heterogeneous TensorFlow Mapper Utilizing Bayesian Optimization and Genetic Algorithms.
ACM Trans. Intell. Syst. Technol., 2020

IRHT: An SDC detection and recovery architecture based on value locality of instruction binary codes.
Microprocess. Microsystems, 2020

Flow mapping on mesh-based deep learning accelerator.
J. Parallel Distributed Comput., 2020

Effects of Approximate Multiplication on Convolutional Neural Networks.
CoRR, 2020

Divisible load scheduling of image processing applications on the heterogeneous star and tree networks using a new genetic algorithm.
Concurr. Comput. Pract. Exp., 2020

Reliable and Energy Efficient MLC STT-RAM Buffer for CNN Accelerators.
Comput. Electr. Eng., 2020

A novel digital fuzzy system for image edge detection based on wrap-gate carbon nanotube transistors.
Comput. Electr. Eng., 2020

A machine-learning approach to predicting hypotensive events in ICU settings.
Comput. Biol. Medicine, 2020

A Fine-Grained Source-Throttling Method for Mesh Architectures.
IEEE Access, 2020

Partition Pruning: Parallelization-Aware Pruning for Dense Neural Networks.
Proceedings of the 28th Euromicro International Conference on Parallel, 2020

NoC Design Methodologies for Heterogeneous Architecture.
Proceedings of the 28th Euromicro International Conference on Parallel, 2020

Supervised Machine-Learning Algorithms in Real-time Prediction of Hypotensive Events.
Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020

2019
Efficient Mitchell's Approximate Log Multipliers for Convolutional Neural Networks.
IEEE Trans. Computers, 2019

Toward efficient implementation of basic balanced ternary arithmetic operations in CNFET technology.
Microelectron. J., 2019

CLBM: Controlled load-balancing mechanism for congestion management in silicon interposer NoC architecture.
J. Syst. Archit., 2019

A new approach to the Population-Based Incremental Learning algorithm using virtual regions for task mapping on NoCs.
J. Syst. Archit., 2019

Computational storage: an efficient and scalable platform for big data and HPC applications.
J. Big Data, 2019

DICA: destination intensity and congestion-aware output selection strategy for network-on-chip systems.
IET Comput. Digit. Tech., 2019

Novel CNFET ternary circuit techniques for high-performance and energy-efficient design.
IET Circuits Devices Syst., 2019

Partition Pruning: Parallelization-Aware Pruning for Deep Neural Networks.
CoRR, 2019

Catalina: In-Storage Processing Acceleration for Scalable Big Data Analytics.
Proceedings of the 27th Euromicro International Conference on Parallel, 2019

Flow mapping and data distribution on mesh-based deep learning accelerator.
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

A Radiation Hard Sense Circuit for Spin Transfer Torque Random Access Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Accelerating HPC Applications Using Computational Storage Devices.
Proceedings of the 21st IEEE International Conference on High Performance Computing and Communications; 17th IEEE International Conference on Smart City; 5th IEEE International Conference on Data Science and Systems, 2019

Design of Power-Efficient FPGA Convolutional Cores with Approximate Log Multiplier.
Proceedings of the 27th European Symposium on Artificial Neural Networks, 2019

Efficient Deep Neural Networks for Edge Computing.
Proceedings of the 3rd IEEE International Conference on Edge Computing, 2019

Power and Performance Optimal NoC Design for CPU-GPU Architecture Using Formal Models.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

A Cost-Efficient Iterative Truncated Logarithmic Multiplication for Convolutional Neural Networks.
Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019

2018
AROMa: Aging-Aware Deadlock-Free Adaptive Routing Algorithm and Online Monitoring in 3D NoCs.
IEEE Trans. Parallel Distributed Syst., 2018

Ultra-Efficient Fuzzy Min/Max Circuits Based on Carbon Nanotube FETs.
IEEE Trans. Fuzzy Syst., 2018

Design and Evaluation of a Spintronic In-Memory Processing Platform for Nonvolatile Data Encryption.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

A Compositional Approach for Verifying Protocols Running on On-Chip Networks.
IEEE Trans. Computers, 2018

LEAD: An Adaptive 3D-NoC Routing Algorithm with Queuing-Theory Based Analytical Verification.
IEEE Trans. Computers, 2018

STABLE: Stress-Aware Boolean Matching to Mitigate BTI-Induced SNM Reduction in SRAM-Based FPGAs.
IEEE Trans. Computers, 2018

First-Last: A Cost-Effective Adaptive Routing Solution for TSV-Based Three-Dimensional Networks-on-Chip.
IEEE Trans. Computers, 2018

Energy and performance-aware application mapping for inhomogeneous 3D networks-on-chip.
J. Syst. Archit., 2018

Design and Power Analysis of New Coplanar One-Bit Full-Adder Cell in Quantum-Dot Cellular Automata.
J. Low Power Electron., 2018

System-Level Analysis of 3D ICs with Thermal TSVs.
ACM J. Emerg. Technol. Comput. Syst., 2018

An energy and area efficient 4: 2 compressor based on FinFETs.
Integr., 2018

Hospital enterprise Architecture Framework (Study of Iranian University Hospital Organization).
Int. J. Medical Informatics, 2018

Reducing bypass-based network-on-chip latency using priority mechanism.
IET Comput. Digit. Tech., 2018

Application partitioning and mapping for bypass channel based NoC.
Comput. Electr. Eng., 2018

Simulation-Based Evaluation Strategy for Task Mapping Approaches in WNoC Platforms.
Proceedings of the 26th Euromicro International Conference on Parallel, 2018

Divisible Load Scheduling of Image Processing Applications on the Heterogeneous Star Network Using a new Genetic Algorithm.
Proceedings of the 26th Euromicro International Conference on Parallel, 2018

CompStor: An In-storage Computation Platform for Scalable Distributed Processing.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

HTF-MPR: A heterogeneous TensorFlow mapper targeting performance using genetic algorithms and gradient boosting regressors.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Low-power implementation of Mitchell's approximate logarithmic multiplication for convolutional neural networks.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
A General Fault-Tolerant Minimal Routing for Mesh Architectures.
IEEE Trans. Computers, 2017

Deadlock Verification of Cache Coherence Protocols and Communication Fabrics.
IEEE Trans. Computers, 2017

SENSIBle: A Highly Scalable SENsor DeSIgn for Path-Based Age Monitoring in FPGAs.
IEEE Trans. Computers, 2017

A Single Parity-Check Digit for One Trit Error Detection in Ternary Communication Systems: Gate-Level and Transistor-Level Designs.
J. Multiple Valued Log. Soft Comput., 2017

Quantum-dot cellular automata circuits with reduced external fixed inputs.
Microprocess. Microsystems, 2017

Towards Approximate Computing with Quantum-Dot Cellular Automata.
J. Low Power Electron., 2017

High-performance ternary operators for scrambling.
Integr., 2017

Method for designing ternary adder cells based on CNFETs.
IET Circuits Devices Syst., 2017

A new approach for designing compressors with a new hardware-friendly mathematical method for multi-input XOR gates.
IET Circuits Devices Syst., 2017

Online monitoring and adaptive routing for aging mitigation in NoCs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Performance and Energy Aware Inhomogeneous 3D Networks-on-Chip Architecture Generation.
IEEE Trans. Parallel Distributed Syst., 2016

Capacitive and Inductive TSV-to-TSV Resilient Approaches for 3D ICs.
IEEE Trans. Computers, 2016

Loss-Aware Switch Design and Non-Blocking Detection Algorithm for Intra-Chip Scale Photonic Interconnection Networks.
IEEE Trans. Computers, 2016

A Resilient Routing Algorithm with Formal Reliability Analysis for Partially Connected 3D-NoCs.
IEEE Trans. Computers, 2016

Ternary cyclic redundancy check by a new hardware-friendly ternary operator.
Microelectron. J., 2016

An Efficient Analog-to-Digital Converter Based on Carbon Nanotube FETs.
J. Low Power Electron., 2016

Design of quaternary 4-2 and 5-2 compressors for nanotechnology.
Comput. Electr. Eng., 2016

Introduction to the Special Section on On-chip parallel and network-based systems.
Comput. Electr. Eng., 2016

CoBRA: Low cost compensation of TSV failures in 3D-NoC.
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

ADVOCAT: Automated deadlock verification for on-chip cache coherence and interconnects.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Coupling Mitigation in 3-D Multiple-Stacked Devices.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Advances in multicore systems architectures.
J. Supercomput., 2015

Design and analysis of a mesh-based wireless network-on-chip.
J. Supercomput., 2015

Analytical Fault Tolerance Assessment and Metrics for TSV-Based 3D Network-on-Chip.
IEEE Trans. Computers, 2015

Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach.
Microelectron. J., 2015

Designing quantum-dot cellular automata counters with energy consumption analysis.
Microprocess. Microsystems, 2015

An Ultra-High Speed and Low Complexity Quantum-Dot Cellular Automata Full Adder.
J. Low Power Electron., 2015

Analytical Reliability Analysis of 3D NoC under TSV Failure.
ACM J. Emerg. Technol. Comput. Syst., 2015

Design and Verification of New n-Bit Quantum-Dot Synchronous Counters Using Majority Function-Based JK Flip-Flops.
J. Circuits Syst. Comput., 2015

On the design of hybrid routing mechanism for mesh-based network-on-chip.
Integr., 2015

On-chip parallel and network-based systems.
Integr., 2015

Voltage mirror circuit by carbon nanotube field effect transistors for mirroring dynamic random access memories in multiple-valued logic and fuzzy logic.
IET Circuits Devices Syst., 2015

Using constraint programming for the design of network-on-chip architectures.
Computing, 2015

Special issue on on-chip parallel and network-based systems.
Computing, 2015

Capacitive Coupling Mitigation for TSV-based 3D ICs.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

An Adaptive, Low Restrictive and Fault Resilient Routing Algorithm for 3D Network-on-Chip.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

Accurate System-level TSV-to-TSV Capacitive Coupling Fault Model for 3D-NoC.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

2014
High-Efficient Circuits for Ternary Addition.
VLSI Design, 2014

Ultra-low-power adder stage design for exascale floating point units.
ACM Trans. Embed. Comput. Syst., 2014

Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Network-on-Chip.
Microprocess. Microsystems, 2014

Novel Robust Single Layer Wire Crossing Approach for Exclusive OR Sum of Products Logic Design with Quantum-Dot Cellular Automata.
J. Low Power Electron., 2014

Voltage island based heterogeneous NoC design through constraint programming.
Comput. Electr. Eng., 2014

A GALS Router for Asynchronous Network-on-Chip.
Proceedings of the 2nd International Workshop on Many-core Embedded Systems, 2014

TSV-to-TSV inductive coupling-aware coding scheme for 3D Network-on-Chip.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

2013
Efficient multicast schemes for 3-D Networks-on-Chip.
J. Syst. Archit., 2013

From UML specifications to mapping and scheduling of tasks into a NoC, with reliability considerations.
J. Syst. Archit., 2013

Scalable load balancing congestion-aware Network-on-Chip router architecture.
J. Comput. Syst. Sci., 2013

Multicore computing systems: Architecture, programming tools, and applications.
J. Comput. Syst. Sci., 2013

Contention-aware selection strategy for application-specific network-on-chip.
IET Comput. Digit. Tech., 2013

Quality of Service Optimization for Network-on-Chip Using Bandwidth-Constraint Mapping Algorithm.
Proceedings of the 21st Euromicro International Conference on Parallel, 2013

CPNoC: On Using Constraint Programming in Design of Network-on-Chip Architecture.
Proceedings of the 21st Euromicro International Conference on Parallel, 2013

On heterogeneous network-on-chip design based on constraint programming.
Proceedings of the Network on Chip Architectures, 2013

2012
A software pipelining algorithm of streaming applications with low buffer requirements.
Sci. Iran., 2012

A load-balanced congestion-aware wireless network-on-chip design for multi-core platforms.
Microprocess. Microsystems, 2012

Editorial notes: Special issue on on-chip parallel and network-based systems.
Microprocess. Microsystems, 2012

Mapping and Scheduling in Heterogeneous NoC through Population-Based Incremental Learning.
J. Univers. Comput. Sci., 2012

High-throughput differentiated service provision router architecture for wireless network-on-chip.
Int. J. High Perform. Syst. Archit., 2012

Parallel low-density parity check decoding on a network-on-chip-based multiprocessor platform.
IET Comput. Digit. Tech., 2012

Design and evaluation of a high throughput robust router for network-on-chip.
IET Comput. Digit. Tech., 2012

A formally verified deadlock-free routing function in a fault-tolerant NoC architecture.
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

LATEX: New Selection Policy for Adaptive Routing in Application-Specific NoC.
Proceedings of the 20th Euromicro International Conference on Parallel, 2012

2011
Area and power-efficient innovative congestion-aware Network-on-Chip architecture.
J. Syst. Archit., 2011

Special issue on: On-chip parallel and network-based systems.
J. Syst. Archit., 2011

A scheduling approach for distributed resource architectures with scarce communication resources.
Int. J. High Perform. Syst. Archit., 2011

Load Balancing for Data-Parallel Applications on Network-on-Chip Enabled Multi-processor Platform.
Proceedings of the 19th International Euromicro Conference on Parallel, 2011

A Wireless Network-on-Chip Design for Multicore Platforms.
Proceedings of the 19th International Euromicro Conference on Parallel, 2011

2010
Parallel processing for block ciphers on a fault tolerant networked processor array.
Int. J. High Perform. Syst. Archit., 2010

Area and Power-efficient Innovative Network-on-Chip Architecurte.
Proceedings of the 18th Euromicro Conference on Parallel, 2010

A scalable delay insensitive asynchronous NoC with adaptive routing.
Proceedings of the 17th International Conference on Telecommunications, 2010

Message Driven Programming with S-Net: Methodology and Performance.
Proceedings of the 39th International Conference on Parallel Processing, 2010

2009
A framework for low energy data management in reconfigurable multi-context architectures.
J. Syst. Archit., 2009

Parallel FFT Algorithms on Network-on-Chips.
J. Circuits Syst. Comput., 2009

Performance Impact of Task-to-Task Communication Protocol in Network-on-Chip.
J. Circuits Syst. Comput., 2009

A variable frequency link for a power-aware network-on-chip (NoC).
Integr., 2009

Optimisations for LocSens - an indoor location tracking system using wireless sensors.
Int. J. Sens. Networks, 2009

A high level power model for Network-on-Chip (NoC) router.
Comput. Electr. Eng., 2009

Resource management and task partitioning and scheduling on a run-time reconfigurable embedded system.
Comput. Electr. Eng., 2009

Parallel LDPC Decoding on a Network-on-Chip Based Multiprocessor Platform.
Proceedings of the 21st International Symposium on Computer Architecture and High Performance Computing, 2009

Parallel and Pipeline Processing for Block Cipher Algorithms on a Network-on-Chip.
Proceedings of the Sixth International Conference on Information Technology: New Generations, 2009

Scheduling Techniques for Multi-Core Architectures.
Proceedings of the Sixth International Conference on Information Technology: New Generations, 2009

Low power adaptive pipeline based on instruction isolation.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Mobile Agents for Wireless Sensor Networks.
Proceedings of the 2009 International Conference on Wireless Networks, 2009

2008
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture.
Parallel Process. Lett., 2008

An ASIC design and formal analysis of a novel pipelined and parallel sorting accelerator.
Integr., 2008

Scheduling methodology for conditional execution of kernels onto multicontext reconfigurable architectures.
IET Comput. Digit. Tech., 2008

Design of simulation and analytical models for a 2D-meshed asymmetric adaptive router.
IET Comput. Digit. Tech., 2008

RECFEC: A Reconfigurable FEC Processor for Viterbi, Turbo, Reed-Solomon and LDPC Coding.
Proceedings of the WCNC 2008, IEEE Wireless Communications & Networking Conference, March 31 2008, 2008

Parallel FFT Algorithms on Network-on-Chips.
Proceedings of the Fifth International Conference on Information Technology: New Generations (ITNG 2008), 2008

Self-optimized Routing in a Network on-a-Chip.
Proceedings of the Biologically-Inspired Collaborative Computing, 2008

ESTR - Energy Saving Token Ring Protocol for Wireless Sensor Networks.
Proceedings of the 2008 International Conference on Wireless Networks, 2008

LocSens - An Indoor Location Tracking System using Wireless Sensors.
Proceedings of the 17th International Conference on Computer Communications and Networks, 2008

Efficient Parallel Buffer Structure and Its Management Scheme for a Robust Network-on-Chip (NoC) Architecture.
Proceedings of the Advances in Computer Science and Engineering, 2008

Specific Absorption Rate Calculation using Parallel 3D Finite Difference Time Domain Technique.
Proceedings of the 2008 International Conference on Communications in Computing, 2008

A Generic Network Interface Architecture for a Networked Processor Array (NePA).
Proceedings of the Architecture of Computing Systems, 2008

2007
Ultra-fast and efficient algorithm for energy optimization by gradient-based stochastic voltage and task scheduling.
ACM Trans. Design Autom. Electr. Syst., 2007

Design of a router for network-on-chip.
Int. J. High Perform. Syst. Archit., 2007

Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP).
Proceedings of the 19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 2007

On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture.
Proceedings of the Fourth International Conference on Information Technology: New Generations (ITNG 2007), 2007

Application of a Heterogeneous Reconfigurable Architecture to OFDM Wireless Systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Modulo Scheduling Algorithm for a Coarse-Grain Reconfigurable Array Template.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Configuration and Data Scheduling for Executing Dynamic Applications onto Multi-Context Reconfigurable Architectures.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

Integrating Power Management into Distributed Real-time Systems at Very Low Implementation Cost.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

A Reconfigurable Processor for Forward Error Correction.
Proceedings of the Architecture of Computing Systems, 2007

2006
A Multi-Standard Viterbi Decoder for Mobile Applications Using a Reconfigurable Architecture.
Proceedings of the 64th IEEE Vehicular Technology Conference, 2006

A Reconfigurable Architecture for Wireless Communication Systems.
Proceedings of the Third International Conference on Information Technology: New Generations (ITNG 2006), 2006

Configuration Scheduling for Conditional Branch Execution Onto Multi-Context Reconfigurable Architectures.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys).
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

Increasing the throughput of an adaptive router in network-on-chip (NoC).
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

2005
Low Power Data Prefetch for 3D Image Applications on Coarse-Grain Reconfigurable Architectures.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

An Approach to Execute Conditional Branches onto SIMD Multi-Context Reconfigurable Architectures.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

A Programmable DSP Architecture for Wireless Communication Systems.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
Fast parallel soft Viterbi decoder mapping on a reconfigurable DSP platform.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Efficient mapping of hierarchical trees on coarse-grain reconfigurable architectures.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

MaRS: a macro-pipelined reconfigurable system.
Proceedings of the First Conference on Computing Frontiers, 2004

Fast and efficient voltage scheduling by evolutionary slack distribution.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Automatic compilation to a coarse-grained reconfigurable system-opn-chip.
ACM Trans. Embed. Comput. Syst., 2003

Algorithm optimizations and mapping scheme for interactive ray tracing on a reconfigurable architecture.
Comput. Graph., 2003

Fast Parallel FFT on a Reconfigurable Computation Platform.
Proceedings of the 15th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2003), 2003

Camera calibration of long image sequences with the presence of occlusions.
Proceedings of the 2003 International Conference on Image Processing, 2003

Persepolis: Recovering history with a handheld camera.
Proceedings of the 24th Annual Conference of the European Association for Computer Graphics, 2003

A Component Oriented Simulator for HW/SW Co-Designs.
Proceedings of the First Workshop on Embedded Systems for Real-Time Multimedia, 2003

Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures.
Proceedings of the 2003 Design, 2003

Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver.
Proceedings of the 2003 Design, 2003

Interactive Ray Tracing on Reconfigurable SIMD MorphoSys.
Proceedings of the 2003 Design, 2003

A fast parallel reed-solomon decoder on a reconfigurable architecture.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

Adaptive computing: what can it do, where can it go?
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Topology selection for energy minimization in embedded networks.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Interactive Ray Tracing on Reconfigurable SIMD Morphosys.
Proceedings of the Embedded Software for SoC, 2003

2002
IMPACCT: Methodology and Tools for Power-Aware Embedded Systems.
Des. Autom. Embed. Syst., 2002

Mode Selection and Mode-Dependency Modeling for Power-Aware Embedded Systems.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Interactive Ray Tracing Using a SIMD Reconfigurable Architecture.
Proceedings of the 14th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2002), 2002

Power-Aware Task Motion for Enhancing Dynamic Range of Embedded Systems with Renewable Energy Sources.
Proceedings of the Power-Aware Computer Systems, Second International Workshop, 2002

Recovering 3D Metric Structure and Motion from Multiple Uncalibrated Cameras.
Proceedings of the 2002 International Symposium on Information Technology (ITCC 2002), 2002

Combined Functional Partitioning and Communication Speed Selection for Networked Voltage-Scalable Processors.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

MorphoSys: A Coarse Grain Reconfigurable Architecture for Multimedia Applications (Research Note).
Proceedings of the Euro-Par 2002, 2002

A Novel Predication Scheme for a SIMD System-on-Chip.
Proceedings of the Euro-Par 2002, 2002

Improving the Operation Autonomy of SIMD Processing Elements by Using Guarded Instructions and Pseudo Branches.
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

A Complete Data Scheduler for Multi-Context Reconfigurable Architectures.
Proceedings of the 2002 Design, 2002

Communication speed selection for embedded systems with networked voltage-scalable processors.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

2001
A framework for reconfigurable computing: task scheduling and context management.
IEEE Trans. Very Large Scale Integr. Syst., 2001

A formal approach to context scheduling for multicontext reconfigurable architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2001

Kernel scheduling techniques for efficient solution space exploration in reconfigurable computing.
J. Syst. Archit., 2001

Design and implementation of Automatic Parallel Detection Layer.
Proceedings of the IEEE International Conference on Systems, 2001

A data scheduler for multi-context reconfigurable architectures.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems.
Proceedings of the 38th Design Automation Conference, 2001

A constraint-based application model and scheduling techniques for power-aware systems.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture.
Proceedings of the 2001 International Conference on Compilers, 2001

2000
Design and Implementation of the MorphoSys Reconfigurable Computing Processor.
J. VLSI Signal Process., 2000

<i>MorphoSys</i>: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications.
IEEE Trans. Computers, 2000

Guest Editors' Introduction: Configurable Computing.
IEEE Des. Test Comput., 2000

Configuration Management in Multi-Context Reconfigurable Systems for Simultaneous Performance and Power Optimization.
Proceedings of the 13th International Symposium on System Synthesis, 2000

Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

MorphoSys: case study of a reconfigurable computing system targeting multimedia applications.
Proceedings of the 37th Conference on Design Automation, 2000

1999
A Framework for Scheduling and Context Allocation in Reconfigurable Computing.
Proceedings of the 12th International Symposium on System Synthesis, 1999

MorphoSys: A Reconfigurable Processor Trageted to High Performance Image Application.
Proceedings of the Parallel and Distributed Processing, 1999

The MorphoSys Parallel Reconfigurable System.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

The MorphoSys Dynamically Reconfigurable System-on-Chip.
Proceedings of the 1st NASA / DoD Workshop on Evolvable Hardware (EH '99), 1999

Kernel Scheduling in Reconfigurable Computing.
Proceedings of the 1999 Design, 1999

1998
Modeled and Measured Instruction Fetching Performance for Superscalar Microprocessors.
IEEE Trans. Parallel Distributed Syst., 1998

Low Expansion Packings and Embeddings of Hypercubes into Star Graphs: A Performance-Oriented Approach.
IEEE Trans. Parallel Distributed Syst., 1998

Faster column operations in star networks.
Telecommun. Syst., 1998

A parallel algorithm for pulsed laser infrared tomography.
Pattern Recognit. Lett., 1998

A scalable register file architecture for superscalar processors.
Microprocess. Microsystems, 1998

1997
On Embedding Rings into a Star-Related Network.
Inf. Sci., 1997

Multiple Branch and Block Prediction.
Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), 1997

1996
Embedding an Arbitrary Binary Tree into the Star Graph.
IEEE Trans. Computers, 1996

A Grid Embedding into the Star Graph for Image Analysis Solutions.
Inf. Process. Lett., 1996

Some Topological Properties of Star Connected Cycles.
Inf. Process. Lett., 1996

Average distance and routing algorithms in the star-connected cycles interconnection network.
Proceedings of the Eighth IEEE Symposium on Parallel and Distributed Processing, 1996

Hamiltonicity of the Clustered-Star Graph with Embedding Applications.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1996

Performance Study of a Multithreaded Superscalar Microprocessor.
Proceedings of the Second International Symposium on High-Performance Computer Architecture, 1996

Instruction Fetching Mechanisms for Superscalar Microprocessors.
Proceedings of the Euro-Par '96 Parallel Processing, 1996

Variable-Dilation Embeddings of Hypercubes into Star Graphs: Performance Metrics, Mapping Functions, and Routing.
Proceedings of the Euro-Par '96 Parallel Processing, 1996

A scalable register file architecture for dynamically scheduled processors.
Proceedings of the Fifth International Conference on Parallel Architectures and Compilation Techniques, 1996

A fine-grain multithreading superscalar architecture.
Proceedings of the Fifth International Conference on Parallel Architectures and Compilation Techniques, 1996

1995
A Well-Behaved Enumeration of Star Graphs.
IEEE Trans. Parallel Distributed Syst., 1995

Performance issues of a superscalar microprocessor.
Microprocess. Microsystems, 1995

Broadcasting Algorithms for the Star-Connected Cycles Interconnection Network.
J. Parallel Distributed Comput., 1995

Design and implementation of a 100 MHz centralized instruction window for a superscalar microprocessor.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Fault-diameter of the star-connected cycles interconnection network.
Proceedings of the 28th Annual Hawaii International Conference on System Sciences (HICSS-28), 1995

1994
Incomplete Star: An Incrementally Scalable Network Based on the Star Graph.
IEEE Trans. Parallel Distributed Syst., 1994

Pipelining and Bypassing in a VLIW Processor.
IEEE Trans. Parallel Distributed Syst., 1994

A performance comparison of several superscalar processor models with a VLIW processor.
Microprocess. Microsystems, 1994

A New Approach for Circle Detection on Multiprocessors.
J. Parallel Distributed Comput., 1994

Pyramid simulation of image processing applications.
Image Vis. Comput., 1994

Parallel Algorithms for Line Detection on A Pyramid Architecture.
Int. J. Pattern Recognit. Artif. Intell., 1994

1993
A Systematic Approch for Mapping Application Tasks in Hypercubes.
IEEE Trans. Computers, 1993

A Routing and Broadcasting Scheme on Faulty Star Graphs.
IEEE Trans. Computers, 1993

The Clustered-Star Graph: A New Topology for Large Interconnection Networks.
Proceedings of the Seventh International Parallel Processing Symposium, 1993

The Star Connected Cycles: A Fixed-Degree Network for Parallel Processing.
Proceedings of the 1993 International Conference on Parallel Processing, 1993

1992
Finding circular shapes in an image on a pyramid architecture.
Pattern Recognit. Lett., 1992

Design and implementation of the 'Tiny RISC' microprocessor.
Microprocess. Microsystems, 1992

Performance analysis and design methodology for a scalable superscalar architecture.
Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

Parallel Implementation of the Auction Algorithm on the Intel Hypercube.
Proceedings of the 6th International Parallel Processing Symposium, 1992

On Design and Performance Analysis of a Superscalar Architecture.
Proceedings of the 1992 International Conference on Parallel Processing, 1992

Optimal Ring Embedding in Hypercubes with Faulty Links.
Proceedings of the Digest of Papers: FTCS-22, 1992

1991
A Parallel Asynchronous Garbage Collection Algorithm for Distributed Systems.
IEEE Trans. Knowl. Data Eng., 1991

Special Features of a VLIW Architecture.
Proceedings of the Fifth International Parallel Processing Symposium, Proceedings, Anaheim, California, USA, April 30, 1991

Hypermesh: A Combined Quad Tree and Mesh Network for Parallel Processing.
Proceedings of the International Conference on Parallel Processing, 1991

Parallel Hough Transform for Image Processing on a Pyramid Architecture.
Proceedings of the International Conference on Parallel Processing, 1991

A Percolation Based VLIW Architecture.
Proceedings of the International Conference on Parallel Processing, 1991

1990
Near-optimal message routing and broadcasting in faulty hypercubes.
Int. J. Parallel Program., 1990

1987
Performance of symbolic applications on a parallel architecture.
Int. J. Parallel Program., 1987

1986
Software Authorization Systems.
IEEE Softw., 1986

1985
Network Facility for a Reconfigurable Computer Architecture.
Proceedings of the 5th International Conference on Distributed Computing Systems, 1985


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