Jung-Pil Lim

According to our database1, Jung-Pil Lim authored at least 2 papers between 2020 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
A Source-Driver IC Including Power-Switching Fast-Slew-Rate Buffer and 8Gb/s Effective 3-Tap DFE Receiver Achieving 4.9mV DVRMS and 17V/ps Slew Rate for 8K Displays and Beyond.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2020
An Analytical Jitter Tolerance Model for DLL-Based Clock and Data Recovery Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2020


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