Junyong Deng

Orcid: 0000-0002-0823-6371

According to our database1, Junyong Deng authored at least 12 papers between 2009 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Watermarking-based remote secure sequential fusion estimation under the event-triggered mechanism.
J. Frankl. Inst., 2024

2023
DMPRA: A Dynamic Reconfiguration Mechanism for a Dual-Mode Programmable Reconfigurable Array Architecture.
J. Circuits Syst. Comput., June, 2023

Design and Memory Access Optimization of Graph processing Processor design Based on RISC-V.
Proceedings of the 6th International Conference on Artificial Intelligence and Pattern Recognition, 2023

Design and Implementation of SSSP Accelerator based-on Reconfigurable and Programmable Computing Array.
Proceedings of the 6th International Conference on Artificial Intelligence and Pattern Recognition, 2023

2021
Performance Characterization of Rasterization Algorithms for Reconfigurable Graphics Processor.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2021

2020
Demystifying graph processing frameworks and benchmarks.
Sci. China Inf. Sci., 2020

2019
UT-LCA/Scalability-Phase-Simpoint-of-SPEC-CPU2017: SPEC CPU2017 Integer Speed Suite SimPoint Pinballs.
Dataset, August, 2019

UT-LCA/Scalability-Phase-Simpoint-of-SPEC-CPU2017: SPEC CPU2017 Integer Speed Suite SimPoint Pinballs.
Dataset, August, 2019

NPFONoC: A Low-loss, Non-blocking, Scalable Passive Optical Interconnect Network-on-Chip Architecture.
Proceedings of the 2019 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2019

2018
Invited Paper for the Hot Workloads Special Session Hot Regions in SPEC CPU2017.
Proceedings of the 2018 IEEE International Symposium on Workload Characterization, 2018

2016
A parallel implementation of deblocking filter based on video array architecture for HEVC.
Proceedings of the Seventh International Green and Sustainable Computing Conference, 2016

2009
Design of Multi-phase Clock Generation and Selection Circuit for CDR.
Proceedings of the CSIE 2009, 2009 WRI World Congress on Computer Science and Information Engineering, March 31, 2009


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