Shuang Song

Affiliations:
  • University of Texas at Austin, TX, USA


According to our database1, Shuang Song authored at least 20 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
Characterizing the Performance of Emerging Deep Learning, Graph, and High Performance Computing Workloads Under Interference.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024

2020
Demystifying graph processing frameworks and benchmarks.
Sci. China Inf. Sci., 2020

Accelerating Force-directed Graph Layout with Processing-in-Memory Architecture.
Proceedings of the 27th IEEE International Conference on High Performance Computing, 2020

2019
UT-LCA/Scalability-Phase-Simpoint-of-SPEC-CPU2017: SPEC CPU2017 Integer Speed Suite SimPoint Pinballs.
Dataset, August, 2019

UT-LCA/Scalability-Phase-Simpoint-of-SPEC-CPU2017: SPEC CPU2017 Integer Speed Suite SimPoint Pinballs.
Dataset, August, 2019

A Study of Core Utilization and Residency in Heterogeneous Smart Phone Architectures.
Proceedings of the 2019 ACM/SPEC International Conference on Performance Engineering, 2019

Can we trust profiling results?: understanding and fixing the inaccuracy in modern profilers.
Proceedings of the ACM International Conference on Supercomputing, 2019

2018
Start Late or Finish Early: A Distributed Graph Processing System with Redundancy Reduction.
Proc. VLDB Endow., 2018

Invited Paper for the Hot Workloads Special Session Hot Regions in SPEC CPU2017.
Proceedings of the 2018 IEEE International Symposium on Workload Characterization, 2018

Puzzle Memory: Multifractional Partitioned Heterogeneous Memory Scheme.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

Wait of a Decade: Did SPEC CPU 2017 Broaden the Performance Horizon?
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017
CSALT: context switch aware large TLB.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Rethinking TLB Designs in Virtualized Environments: A Very Large Part-of-Memory TLB.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

Fine-Grain Program Snippets Generator for Mobile Core Design.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Sampling-based binary-level cross-platform performance estimation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Genesys: Automatically generating representative training sets for predictive benchmarking.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Proxy-Guided Load Balancing of Graph Processing Workloads on Heterogeneous Clusters.
Proceedings of the 45th International Conference on Parallel Processing, 2016

Fine-grained power analysis of emerging graph processing workloads for cloud operations management.
Proceedings of the 2016 IEEE International Conference on Big Data (IEEE BigData 2016), 2016

2015
Data partitioning strategies for graph workloads on heterogeneous clusters.
Proceedings of the International Conference for High Performance Computing, 2015

GPGPU Benchmark Suites: How Well Do They Sample the Performance Spectrum?
Proceedings of the 44th International Conference on Parallel Processing, 2015


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