K. Parthasarathy

According to our database, K. Parthasarathy authored at least 7 papers between 1985 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2014

Phase space frames and frame operators.

T. C. Easwaran Nambudiri, K. Parthasarathy

Int. J. Wavelets Multiresolution Inf. Process., 2014

1994

A Methodology for Architecture Synthesis of Cascaded IIR Filters on TLU FPGAs.

G. N. Rathna, S. K. Nandy, K. Parthasarathy

Proceedings of the Seventh International Conference on VLSI Design, 1994

TWTXBB: A Low Latency, High Throughput Multiplier Architecture Using a New 4 --> 2 Compressor.

Debabrata Ghosh, S. K. Nandy, K. Parthasarathy

Proceedings of the Seventh International Conference on VLSI Design, 1994

1993

NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs.

Debabrata Ghosh, S. K. Nandy, K. Parthasarathy, V. Visvanathan

Proceedings of the Sixth International Conference on VLSI Design, 1993

Architectural Synthesis of Performance-Driven Multipliers with Accumulator Interleaving.

Debabrata Ghosh, S. K. Nandy, P. Sadayappan, K. Parthasarathy

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1987

On the direct parallel solution of systems of linear equations: New algorithms and systolic structures.

M. K. Sridhar, R. Srinath, K. Parthasarathy

Inf. Sci., 1987

1985

Simplified algorithms based on Haar transforms for signal recognition in protective relays.

D. B. Fakruddin, K. Parthasarathy

Proc. IEEE, 1985