Debabrata Ghosh
Orcid: 0000-0002-4603-1238
According to our database1,
Debabrata Ghosh
authored at least 24 papers
between 1993 and 2024.
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Bibliography
2024
Finding correlation between diabetic retinopathy and diabetes during pregnancy based on computer-aided diagnosis: a review.
Multim. Tools Appl., March, 2024
2020
Product greening and pricing strategies of firms under green sensitive consumer demand and environmental regulations.
Ann. Oper. Res., 2020
2019
Integrated product design, shelf-space allocation and transportation decisions in green supply chains.
Int. J. Prod. Res., 2019
Sponsored search advertising and dynamic pricing for perishable products under inventory-linked customer willingness to pay.
Eur. J. Oper. Res., 2019
2016
A robust iterative super-resolution mosaicking algorithm using an adaptive and directional Huber-Markov regularization.
J. Vis. Commun. Image Represent., 2016
2014
Robust Spatial-Domain Based Super-Resolution Mosaicing of CubeSat Video Frames: Algorithm and Evaluation.
Comput. Inf. Sci., 2014
2013
A randomized methodology for post-silicon validation of CAN and other communication modules.
Proceedings of the International Conference on Advances in Computing, 2013
2012
Proceedings of the 2012 IEEE International Conference on Electro/Information Technology, 2012
Proceedings of the Intelligent Robots and Computer Vision XXIX: Algorithms and Techniques, 2012
2011
Differential Evolution using Jumping Genes Adaptation.
Proceedings of the 5th Indian International Conference on Artificial Intelligence, 2011
2001
Heuristics, Experimental Subjects, and Treatment Evaluation in Bigraph Crossing Minimization.
ACM J. Exp. Algorithmics, 2001
1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the Algorithm Engineering and Experimentation, 1999
1998
Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking.
Proceedings of the 1998 Design, 1998
1997
Towards a new benchmarking paradigm in EDA: analysis of equivalence class mutant circuit distributions.
Proceedings of the 1997 International Symposium on Physical Design, 1997
1995
Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology.
IEEE Trans. Very Large Scale Integr. Syst., 1995
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995
1994
Proceedings of the Seventh International Conference on VLSI Design, 1994
TWTXBB: A Low Latency, High Throughput Multiplier Architecture Using a New 4 --> 2 Compressor.
Proceedings of the Seventh International Conference on VLSI Design, 1994
1993
NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs.
Proceedings of the Sixth International Conference on VLSI Design, 1993
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993
Architectural Synthesis of Performance-Driven Multipliers with Accumulator Interleaving.
Proceedings of the 30th Design Automation Conference. Dallas, 1993