Debabrata Ghosh

According to our database1, Debabrata Ghosh authored at least 19 papers between 1993 and 2016.

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Bibliography

2016
A robust iterative super-resolution mosaicking algorithm using an adaptive and directional Huber-Markov regularization.
J. Visual Communication and Image Representation, 2016

A survey on image mosaicing techniques.
J. Visual Communication and Image Representation, 2016

2014
Robust Spatial-Domain Based Super-Resolution Mosaicing of CubeSat Video Frames: Algorithm and Evaluation.
Computer and Information Science, 2014

2013
A randomized methodology for post-silicon validation of CAN and other communication modules.
Proceedings of the International Conference on Advances in Computing, 2013

2012
Quantitative evaluation of image mosaicing in multiple scene categories.
Proceedings of the 2012 IEEE International Conference on Electro/Information Technology, 2012

2011
Differential Evolution using Jumping Genes Adaptation.
Proceedings of the 5th Indian International Conference on Artificial Intelligence, 2011

2001
Heuristics, Experimental Subjects, and Treatment Evaluation in Bigraph Crossing Minimization.
ACM Journal of Experimental Algorithmics, 2001

1999
Evaluating iterative improvement heuristics for bigraph crossing minimization.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Equivalence classes of circuit mutants for experimental design.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Heuristics and Experimental Design for Bigraph Crossing Number Minimization.
Proceedings of the Algorithm Engineering and Experimentation, 1999

1998
Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking.
Proceedings of the 1998 Design, 1998

1997
Towards a new benchmarking paradigm in EDA: analysis of equivalence class mutant circuit distributions.
Proceedings of the 1997 International Symposium on Physical Design, 1997

1995
Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology.
IEEE Trans. VLSI Syst., 1995

Wave pipelined architecture folding: a method to achieve low power and low area.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

1994
A 600MHz Half-Bit Level Pipelined Multiplier Macrocell.
Proceedings of the Seventh International Conference on VLSI Design, 1994

TWTXBB: A Low Latency, High Throughput Multiplier Architecture Using a New 4 --> 2 Compressor.
Proceedings of the Seventh International Conference on VLSI Design, 1994

1993
NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs.
Proceedings of the Sixth International Conference on VLSI Design, 1993

A 400 MHz Wave-Pipelined 8 X 8-Bit Multiplier in CMOS Technology.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Architectural Synthesis of Performance-Driven Multipliers with Accumulator Interleaving.
Proceedings of the 30th Design Automation Conference. Dallas, 1993


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