Kaihang Wang
According to our database1,
Kaihang Wang authored at least 6 papers
between 2023 and 2026.
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Bibliography
2026
12.4 A 21.6fsrms-Jitter, -260.7dB-FoM Fractional-N PLL Enabled by an Intrinsically Linear Variable-Slope SPD for Quantization-Error Cancellation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
12.9 A 10.2-to-16.2GHz Dual-Mode-Transformer-Based Wideband Series-Resonance VCO Achieving >201.1dBc/Hz FoMT at a 10MHz Offset.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
2025
A 37.5fs-rms Jitter and -254.1dB FoM Fractional-N Sampling PLL with Reference-Phase-Selection and Complementary-DTC Achieving 8× DTC Range Reduction and Zero DTC Delay Offset.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
2024
Sensors, July, 2024
J. Real Time Image Process., April, 2024
2023
PRAD: A Bayesian Optimization-based DSE Framework for Parameterized Reconfigurable Architecture Design.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023