Wenbo Yin

According to our database1, Wenbo Yin authored at least 27 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization.
IEEE Trans. Very Large Scale Integr. Syst., March, 2024

2023
CPIC at SemEval-2023 Task 7: GPT2-Based Model for Multi-evidence Natural Language Inference for Clinical Trial Data.
Proceedings of the The 17th International Workshop on Semantic Evaluation, 2023

THRAM: A Template-based Heterogeneous CGRA Modeling Framework Supporting Fast DSE.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A Dynamic Partial Reconfigurable CGRA Framework for Multi-Kernel Applications.
Proceedings of the International Conference on Field Programmable Technology, 2023

GRAFT: GNN-based Adaptive Framework for Efficient CGRA Mapping.
Proceedings of the International Conference on Field Programmable Technology, 2023

E<sup>2</sup>-ACE: An Energy-Efficient Reconfigurable Crypto-Accelerator with Agile End-to-End Toolchain.
Proceedings of the International Conference on Field Programmable Technology, 2023

PRAD: A Bayesian Optimization-based DSE Framework for Parameterized Reconfigurable Architecture Design.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

UPTRA: An Ultra-Parameterized Temporal CGRA Modeling and Optimization.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

2022
A High-Performance and Scalable NVMe Controller Featuring Hardware Acceleration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Knowledge Enhanced Pre-trained Language Model for Product Summarization.
Proceedings of the Natural Language Processing and Chinese Computing, 2022

TRAM: An Open-Source Template-based Reconfigurable Architecture Modeling Framework.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

2021
FastCGRA: A Modeling, Evaluation, and Exploration Platform for Large-Scale Coarse-Grained Reconfigurable Arrays.
Proceedings of the International Conference on Field-Programmable Technology, 2021

A High-performance Open-channel Open-way NAND Flash Controller Architecture.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

2020
FULL-KV: Flexible and Ultra-Low-Latency In-Memory Key-Value Store System Design on CPU-FPGA.
IEEE Trans. Parallel Distributed Syst., 2020

Achieving Flexible, Low-Latency and 100Gbps Line-rate Load Balancing over Ethernet on FPGA.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

High Throughput and Low Latency Multi-Version Management Key-Value Storage Accelerator.
Proceedings of the International Conference on Field-Programmable Technology, 2020

2019
Empowering Female Entrepreneurs at the 2018 WIE ILC Start-Up Pitch Competition [Society News].
IEEE Consumer Electron. Mag., 2019

High-Throughput and Low-Latency Distributed Management Proxy for Key-Value Store Over 100Gbps Ethernet on FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2019

A Low-Latency Multi-Version Key-Value Store Using B-Tree on an FPGA-CPU Platform.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

2018
Ultra-Low Latency and High Throughput Key-Value Store Systems Over Ethernet.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Ultra-Low-Latency and Flexible In-memory Key-Value Store System Design on CPU-FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2018

2017
FPGA acceleration of the scoring process of X!TANDEM for protein identification.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

A high performance real-time edge detection system with NEON.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

A fully-pipelined hash table achieving low-latency and high throughput key-value retrieving system.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
Hardware TCP Offload Engine based on 10-Gbps Ethernet for low-latency network communication.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Memory efficient and high performance key-value store on FPGA using Cuckoo hashing.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2014
No zero padded sparse matrix-vector multiplication on FPGAs.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014


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