Ronghua Ni

Orcid: 0009-0009-3686-7785

According to our database1, Ronghua Ni authored at least 14 papers between 2012 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
An 11.5-GHz 203.7-dBc/Hz FoM<sub>A</sub> Multi-Tap Inductor-Based Single-Core Fixed-Supply Reconfigurable VCO Achieving 8.2-dB PN Scaling.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2026

A 50-Gb/s 0.76 pJ/b NRZ Transmitter With MUX-FFE Combination and Linear Driver in 28-Nm CMOS.
IEEE Access, 2026

12.4 A 21.6fsrms-Jitter, -260.7dB-FoM Fractional-N PLL Enabled by an Intrinsically Linear Variable-Slope SPD for Quantization-Error Cancellation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026

12.9 A 10.2-to-16.2GHz Dual-Mode-Transformer-Based Wideband Series-Resonance VCO Achieving >201.1dBc/Hz FoMT at a 10MHz Offset.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026

2025
An Ultra-Low Power 915 MHz LO with Adaptive Frequency Calibration for IoT Wake-Up Receivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

A 37.5fs-rms Jitter and -254.1dB FoM Fractional-N Sampling PLL with Reference-Phase-Selection and Complementary-DTC Achieving 8× DTC Range Reduction and Zero DTC Delay Offset.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

2019
A 28-nm 75-fs<sub>rms</sub> Analog Fractional- $N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction.
IEEE J. Solid State Circuits, 2019

A Sub-6-GHz 5G New Radio RF Transceiver Supporting EN-DC With 3.15-Gb/s DL and 1.27-Gb/s UL in 14-nm FinFET CMOS.
IEEE J. Solid State Circuits, 2019

A Sub-6GHz 5G New Radio RF Transceiver Supporting EN-DC with 3.15Gb/s DL and 1.27Gb/s UL in 14nm FinFET CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2017
A 14-nm 0.14-ps<sub>rms</sub> Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration.
IEEE J. Solid State Circuits, 2017

24.8 A 14nm fractional-N digital PLL with 0.14psrms jitter and -78dBc fractional spur for cellular RFICs.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2014
A 915MHz, 6Mb/s, 80pJ/b BFSK receiver with -76dBm sensitivity for high data rate wireless sensor networks.
Proceedings of the Symposium on VLSI Circuits, 2014

2013
A 2.4 GHz Hybrid Polyphase Filter Based BFSK Receiver With High Frequency Offset Tolerance for Wireless Sensor Networks.
IEEE J. Solid State Circuits, 2013

2012
A 2.4GHz hybrid PPF based BFSK receiver with ±180ppm frequency offset tolerance for wireless sensor networks.
Proceedings of the Symposium on VLSI Circuits, 2012


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