Kangning Wang
Orcid: 0009-0004-5356-5299Affiliations:
- Institute of Microelectronics of Chinese Academy of Sciences, University of Chinese Academy of Sciences, China
According to our database1,
Kangning Wang
authored at least 7 papers
between 2023 and 2025.
Collaborative distances:
Collaborative distances:
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Bibliography
2025
ITP-PAD: A Timing Monitoring Mechanism for AVS Systems Using Intersection Timing Prediction and Path Activation Detection.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2025
A Self-Calibrated Unified Voltage-and-Frequency Regulator System Design Based on Universal Logic Line Circuit.
IEEE Trans. Very Large Scale Integr. Syst., February, 2025
Erratum: A low-overhead in-situ timing-error prediction technique with wide-voltage-range transition-detector for variation-tolerant digital circuits [IEICE Electronics Express Vol. 20 (2023) No. 11 pp. 20230145].
IEICE Electron. Express, 2025
AO-EDC: An Accuracy-Oriented Error Detection and Correction Scheme for DVFS System Based on Propagation Detection at Half-Path Points.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
2024
A dynamic voltage scaling circuit design based on critical path replica and time warning techniques.
IEICE Electron. Express, 2024
An Ultra-Low-Power Static Contention-Free 25-Transistor True Single-Phase-Clocked Flip-Flop in 55 nm CMOS.
IEEE Access, 2024
2023
A low-overhead in-situ timing-error prediction technique with wide-voltage-range transition-detector for variation-tolerant digital circuits.
IEICE Electron. Express, 2023