Karthik Somayaji Nanjangud Suryanarayana

Orcid: 0000-0002-6937-8082

According to our database1, Karthik Somayaji Nanjangud Suryanarayana authored at least 8 papers between 2021 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
LLM-USO: Large Language Model-Based Universal Sizing Optimizer.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2026

2024
Pareto Optimization of Analog Circuits Using Reinforcement Learning.
ACM Trans. Design Autom. Electr. Syst., March, 2024

Extreme Risk Mitigation in Reinforcement Learning using Extreme Value Theory.
Trans. Mach. Learn. Res., 2024

Learn-by-Compare: Analog Performance Prediction using Contrastive Regression with Design Knowledge.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Semi-supervised Learning of Dynamical Systems with Neural Ordinary Differential Equations: A Teacher-Student Model Approach.
Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024

2023
Uncertainty Aware Deep Learning for Particle Accelerators.
CoRR, 2023

AutoNF: Automated Architecture Optimization of Normalizing Flows with Unconstrained Continuous Relaxation Admitting Optimal Discrete Solution.
Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023

2021
Prioritized Reinforcement Learning for Analog Circuit Optimization With Design Knowledge.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021


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