Peng Li
Orcid: 0000-0003-3548-4589Affiliations:
- University of California, Santa Barbara, CA, USA
- Texas A&M University, College Station, TX, USA
- Carnegie Mellon University, Pittsburgh, PA, USA (PhD 2003)
According to our database1,
Peng Li
authored at least 212 papers
between 2000 and 2024.
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Bibliography
2024
ACM Trans. Design Autom. Electr. Syst., March, 2024
Semi-supervised Learning of Dynamical Systems with Neural Ordinary Differential Equations: A Teacher-Student Model Approach.
Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024
2023
IEEE Trans. Neural Networks Learn. Syst., June, 2023
Exploring Adversarial Attack in Spiking Neural Networks With Spike-Compatible Gradient.
IEEE Trans. Neural Networks Learn. Syst., May, 2023
CoRR, 2023
AutoNF: Automated Architecture Optimization of Normalizing Flows with Unconstrained Continuous Relaxation Admitting Optimal Discrete Solution.
Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023
2022
H2Learn: High-Efficiency Learning Accelerator for High-Accuracy Spiking Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
SaARSP: An Architecture for Systolic-Array Acceleration of Recurrent Spiking Neural Networks.
ACM J. Emerg. Technol. Comput. Syst., 2022
Parallel Time Batching: Systolic-Array Acceleration of Sparse Spiking Neural Computation.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022
2021
Exponential Stabilization of Inertial Memristive Neural Networks With Multiple Time Delays.
IEEE Trans. Cybern., 2021
Skip-Connected Self-Recurrent Spiking Neural Networks With Joint Intrinsic Parameter and Synaptic Weight Training.
Neural Comput., 2021
Composing Recurrent Spiking Neural Networks using Locally-Recurrent Motifs and Risk-Mitigating Architectural Optimization.
CoRR, 2021
Semi-supervised Wafer Map Pattern Recognition using Domain-Specific Data Augmentation and Contrastive Learning.
Proceedings of the IEEE International Test Conference, 2021
Proceedings of the International Joint Conference on Neural Networks, 2021
Systolic-Array Spiking Neural Accelerators with Dynamic Heterogeneous Voltage Regulation.
Proceedings of the International Joint Conference on Neural Networks, 2021
Efficient Biologically-Plausible Training of Spiking Neural Networks with Precise Timing.
Proceedings of the ICONS 2021: International Conference on Neuromorphic Systems 2021, 2021
Backpropagated Neighborhood Aggregation for Accurate Training of Spiking Neural Networks.
Proceedings of the 38th International Conference on Machine Learning, 2021
Prioritized Reinforcement Learning for Analog Circuit Optimization With Design Knowledge.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Reversible Gating Architecture for Rare Failure Detection of Analog and Mixed-Signal Circuits.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Algorithm and Hardware Co-Design for FPGA Acceleration of Hamiltonian Monte Carlo Based No-U-Turn Sampler.
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021
2020
IEEE Trans. Circuits Syst. II Express Briefs, 2020
A smoothing neural network for minimization l1-lp in sparse signal reconstruction with measurement noises.
Neural Networks, 2020
Sliding mode control of neural networks via continuous or periodic sampling event-triggering algorithm.
Neural Networks, 2020
Quantized synchronization of memristive neural networks with time-varying delays via super-twisting algorithm.
Neurocomputing, 2020
Temporal Spike Sequence Learning via Backpropagation for Deep Spiking Neural Networks.
Proceedings of the Advances in Neural Information Processing Systems 33: Annual Conference on Neural Information Processing Systems 2020, 2020
Advanced Outlier Detection Using Unsupervised Learning for Screening Potential Customer Returns.
Proceedings of the IEEE International Test Conference, 2020
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
Variation-Aware Heterogeneous Voltage Regulation for Multi-Core Systems-on-a-Chip with On-Chip Machine Learning.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
Reconfigurable Dataflow Optimization for Spatiotemporal Spiking Neural Computation on Systolic Array Accelerators.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
2019
Power Management for Multicore Processors via Heterogeneous Voltage Regulation and Machine Learning Enabled Adaptation.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Taming the Stability-Constrained Performance Optimization Challenge of Distributed On-Chip Voltage Regulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Energy-efficient FPGA Spiking Neural Accelerators with Supervised and Unsupervised Spike-timing-dependent-Plasticity.
ACM J. Emerg. Technol. Comput. Syst., 2019
Enabling Non-Hebbian Learning in Recurrent Spiking Neural Processors With Hardware-Friendly On-Chip Intrinsic Plasticity.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
Boosting Throughput and Efficiency of Hardware Spiking Neural Accelerators using Time Compression Supporting Multiple Spike Codes.
CoRR, 2019
Deep Neural Networks with Auxiliary-Model Regulated Gating for Resilient Multi-Modal Sensor Fusion.
CoRR, 2019
Spike-Train Level Backpropagation for Training Deep Recurrent Spiking Neural Networks.
Proceedings of the Advances in Neural Information Processing Systems 32: Annual Conference on Neural Information Processing Systems 2019, 2019
Enabling High-Dimensional Bayesian Optimization for Efficient Failure Detection of Analog and Mixed-Signal Circuits.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
Design Space Exploration of Distributed On-Chip Voltage Regulation Under Stability Constraint.
IEEE Trans. Very Large Scale Integr. Syst., 2018
Quantum Inf. Process., 2018
Online Adaptation and Energy Minimization for Hardware Recurrent Spiking Neural Networks.
ACM J. Emerg. Technol. Comput. Syst., 2018
Unified multi-objective mapping for network-on-chip using genetic-based hyper-heuristic algorithms.
IET Comput. Digit. Tech., 2018
Proceedings of the Advances in Neural Information Processing Systems 31: Annual Conference on Neural Information Processing Systems 2018, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
Parallelizable Bayesian optimization for analog and mixed-signal rare failure detection with high coverage.
Proceedings of the International Conference on Computer-Aided Design, 2018
Design and architectural co-optimization of monolithic 3D liquid state machine-based neuromorphic processor.
Proceedings of the 55th Annual Design Automation Conference, 2018
HFMV: hybridizing formal methods and machine learning for verification of analog and mixed-signal circuits.
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
ACM Trans. Design Autom. Electr. Syst., 2017
Energy efficient parallel neuromorphic architectures with approximate arithmetic on FPGA.
Neurocomputing, 2017
Performance and robustness of bio-inspired digital liquid state machines: A case study of speech recognition.
Neurocomputing, 2017
Exploring sparsity of firing activities and clock gating for energy-efficient recurrent spiking neural processors.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
Navigating mobile robots to target in near shortest time using reinforcement learning with spiking neural networks.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
Calcium-modulated supervised spike-timing-dependent plasticity for readout training and sparsification of the liquid state machine.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
Statistical circuit performance dependency analysis via sparse relevance kernel machine.
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Convergence-Boosted Graph Partitioning using Maximum Spanning Trees for Iterative Solution of Large Linear Circuits.
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
Accurate Modeling of Nonideal Low-Power PWM DC-DC Converters Operating in CCM and DCM using Enhanced Circuit-Averaging Techniques.
ACM Trans. Design Autom. Electr. Syst., 2016
Robust and Efficient Transistor-Level Envelope-Following Analysis of PWM/PFM/PSM DC-DC Converters.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Neuromorphic Processors with Memristive Synapses: Synaptic Interface and Architectural Exploration.
ACM J. Emerg. Technol. Comput. Syst., 2016
Using Presilicon Knowledge to Excite Nonlinear Failure Modes in Large Mixed-Signal Circuits.
IEEE Des. Test, 2016
SSO-LSM: A Sparse and Self-Organizing architecture for Liquid State Machine based neural processors.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
Liquid state machine based pattern recognition on FPGA with firing-activity dependent power gating and approximate computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016
Proceedings of the 23rd International Conference on Pattern Recognition, 2016
Multi-harmonic nonlinear modeling of low-power PWM DC-DC converters operating in CCM and DCM.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Distributed on-chip regulation: theoretical stability foundation, over-design reduction and performance optimization.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Relevance vector and feature machine for statistical analog circuit characterization and built-in self-test optimization.
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
A Parallel Digital VLSI Architecture for Integrated Support Vector Machine Training and Classification.
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Decoupling Capacitance Design Strategies for Power Delivery Networks with Power Gating.
ACM Trans. Design Autom. Electr. Syst., 2015
A Digital Liquid State Machine With Biologically Inspired Learning and Its Application to Speech Recognition.
IEEE Trans. Neural Networks Learn. Syst., 2015
Array-Based Approximate Arithmetic Computing: A General Model and Applications to Multiplier and Squarer Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Circuit Performance Classification With Active Learning Guided Sampling for Support Vector Machines.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Neural Networks, 2015
A Reconfigurable Digital Neuromorphic Processor with Memristive Synaptic Crossbar for Cognitive Computing.
ACM J. Emerg. Technol. Comput. Syst., 2015
Proceedings of the NASA Formal Methods - 7th International Symposium, 2015
Leveraging emerging nonvolatile memory in high-level synthesis with loop transformations.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
General-purpose LSM learning processor architecture and theoretically guided design space exploration.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015
2014
Understanding SRAM Stability via Bifurcation Analysis: Analytical Models and Scaling Trends.
ACM Trans. Design Autom. Electr. Syst., 2014
A model for array-based approximate arithmetic computing with application to multiplier and squarer design.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
A unifying and robust method for efficient envelope-following simulation of PWM/PFM DC-DC converters.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014
Leveraging pre-silicon data to diagnose out-of-specification failures in mixed-signal circuits.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
IC power delivery: Voltage regulation and conversion, system-level cooptimization and technology implications.
ACM Trans. Design Autom. Electr. Syst., 2013
Simulation-Assisted Formal Verification of Nonlinear Mixed-Signal Circuits With Bayesian Inference Guidance.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Localized Stability Checking and Design of IC Power Delivery With Distributed Voltage Regulators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
The emergence of abnormal hypersynchronization in the anatomical structural network of human brain.
NeuroImage, 2013
A 0.38 V near/sub-V<sub>T</sub> digitally controlled low-dropout regulator with enhanced power supply noise rejection in 90 nm CMOS process.
IET Circuits Devices Syst., 2013
Proceedings of the International Conference on Social Computing, SocialCom 2013, 2013
A power-efficient on-chip linear regulator assisted by switched capacitors for fast transient regulation.
Proceedings of the International Symposium on Quality Electronic Design, 2013
An energy efficient approximate adder with carry skip for error resilient neuromorphic VLSI systems.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
Verification of digitally-intensive analog circuits via kernel ridge regression and hybrid reachability analysis.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
IEEE ACM Trans. Comput. Biol. Bioinform., 2012
Efficient Identification of Unstable Loops in Large Linear Analog Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Linking brain behavior to underlying cellular mechanisms via large-scale brain modeling and simulation.
Neurocomputing, 2012
Comput. Phys. Commun., 2012
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
A digital neuromorphic VLSI architecture with memristor crossbar synaptic array for machine learning.
Proceedings of the IEEE 25th International SOC Conference, 2012
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
An ultra-low voltage digitally controlled low-dropout regulator with digital background calibration.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Proceedings of the IEEE International Conference on IC Design & Technology, 2012
Verifying dynamic properties of nonlinear mixed-signal circuits via efficient SMT-based techniques.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
Classifying circuit performance using active-learning guided support vector machines.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
Stability assurance and design optimization of large power delivery networks with multiple on-chip voltage regulators.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
2011
Parallel On-Chip Power Distribution Network Analysis on Multi-Core-Multi-GPU Platforms.
IEEE Trans. Very Large Scale Integr. Syst., 2011
ACM Trans. Design Autom. Electr. Syst., 2011
ACM Trans. Design Autom. Electr. Syst., 2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Hierarchical Analog/Mixed-Signal Circuit Optimization Under Process Variations and Tuning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Reduced order modeling of passive and quasi-active dendrites for nervous system simulation.
J. Comput. Neurosci., 2011
Found. Trends Electron. Des. Autom., 2011
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Simulation of large neuronal networks with biophysically accurate models on graphics processors.
Proceedings of the 2011 International Joint Conference on Neural Networks, 2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
High effective-resolution built-in jitter characterization with quantization noise shaping.
Proceedings of the 48th Design Automation Conference, 2011
Proceedings of the 48th Design Automation Conference, 2011
Proceedings of the 48th Design Automation Conference, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Exact Time-Domain Second-Order Adjoint-Sensitivity Computation for Linear Circuit Analysis and Optimization.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Scalable Analysis of Mesh-Based Clock Distribution Networks Using Application-Specific Reduced Order Modeling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Exploring Circuit Adaptation for Yield Optimization of Low-Power All-Digital Phase-Locked Loops.
J. Low Power Electron., 2010
Robust SRAM Design via Joint Sizing and Voltage Optimization Under Dynamic Stability Constraints.
J. Low Power Electron., 2010
Proceedings of the 2010 International Symposium on Physical Design, 2010
On-the-fly runtime adaptation for efficient execution of parallel multi-algorithm circuit simulation.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Separatrices in high-dimensional state space: system-theoretical tangent computation and application to SRAM dynamic stability analysis.
Proceedings of the 47th Design Automation Conference, 2010
Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation.
Proceedings of the 47th Design Automation Conference, 2010
Exploiting reconfigurability for low-cost in-situ test and monitoring of digital PLLs.
Proceedings of the 47th Design Automation Conference, 2010
Parallel program performance modeling for runtime optimization of multi-algorithm circuit simulation.
Proceedings of the 47th Design Automation Conference, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
An On-the-Fly Parameter Dimension Reduction Approach to Fast Second-Order Statistical Static Timing Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
A Parallel Harmonic-Balance Approach to Steady-State and Envelope-Following Simulation of Driven and Autonomous Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
SICE: design-dependent statistical interconnect corner extraction under inter/intra-die variations.
IET Circuits Devices Syst., 2009
Parallel partitioning based on-chip power distribution network analysis using locality acceleration.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
An application-specific adjoint sensitivity analysis framework for clock mesh sensitivity computation.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Gene-regulatory memories: Electrical-equivalent modeling, simulation and parameter identification.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Final-value ODEs: Stable numerical integration and its application to parallel circuit analysis.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009
Parallelizable stable explicit numerical integration for efficient circuit simulation.
Proceedings of the 46th Design Automation Conference, 2009
2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
A Preconditioned Hierarchical Algorithm for Impedance Extraction of Three-Dimensional Structures With Multiple Dielectrics.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
WavePipe: parallel transient simulation of analog and digital circuits on multi-core shared-memory machines.
Proceedings of the 45th Design Automation Conference, 2008
2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
Characterizing Multistage Nonlinear Drivers and Variability for Accurate Timing and Noise Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
A methodology for systematic built-in self-test of phase-locked loops targeting at parametric failures.
Proceedings of the 2007 IEEE International Test Conference, 2007
Achieving Low-Cost Linearity Test and Diagnosis of Sigma Delta ADCs via Frequency-Domain Nonlinear Analysis and Macromodeling.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Reducing the Complexity of VLSI Performance Variation Modeling Via Parameter Dimension Reduction.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Yield-aware analog integrated circuit optimization using geostatistics motivated performance modeling.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Impedance extraction for 3-D structures with multiple dielectrics using preconditioned boundary element method.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
A methodology for timing model characterization for statistical static timing analysis.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Efficient VCO phase macromodel generation considering statistical parametric variations.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
A Framework for Accounting for Process Model Uncertainty in Statistical Static Timing Analysis.
Proceedings of the 44th Design Automation Conference, 2007
Statistical Leakage Power Minimization Using Fast Equi-Slack Shell Based Optimization.
Proceedings of the 44th Design Automation Conference, 2007
Fast Second-Order Statistical Static Timing Analysis Using Parameter Dimension Reduction.
Proceedings of the 44th Design Automation Conference, 2007
Accelerating Harmonic Balance Simulation Using Efficient Parallelizable Hierarchical Preconditioning.
Proceedings of the 44th Design Automation Conference, 2007
Efficient Frequency-Domain Simulation of Massive Clock Meshes Using Parallel Harmonic Balance.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Temperature-Aware Floorplanning of 3-D ICs Considering Thermally Dependent Leakage Power.
J. Low Power Electron., 2006
Critical Path Analysis Considering Temperature, Power Supply Variations and Temperature Induced Leakage.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Practical variation-aware interconnect delay and slew analysis for statistical timing verification.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Performance-oriented statistical parameter reduction of parameterized systems via reduced rank regression.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Proceedings of the 43rd Design Automation Conference, 2006
Model order reduction of linear networks with massive ports via frequency-dependent port packing.
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the 43rd Design Automation Conference, 2006
2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variations.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Variational analysis of large power grids by exploring statistical sampling sharing and spatial locality.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Proceedings of the 2005 Design, 2005
Proceedings of the 2005 Design, 2005
Power grid simulation via efficient sampling-based sensitivity analysis and hierarchical symbolic relaxation.
Proceedings of the 42nd Design Automation Conference, 2005
A behavioral level approach for nonlinear dynamic modeling of voltage-controlled oscillators.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
Proceedings of the 41th Design Automation Conference, 2004
2003
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
Proceedings of the 2003 Design, 2003
Proceedings of the 40th Design Automation Conference, 2003
Proceedings of the 40th Design Automation Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
Proceedings of the 2002 Design, 2002
2000
Proceedings of the Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), 2000