Kaustubh Joshi

Orcid: 0000-0002-8981-5219

Affiliations:

Intel Corporation, LTD Quality and Reliability, Hillsboro, OR, USA
Taiwan Semiconductor Manufacturing Company, Quality and Reliability, Hsinchu, Taiwan
Indian Institute of Technology Bombay, Department of Electrical Engineering, Mumbai, India

According to our database¹, Kaustubh Joshi authored at least 4 papers between 2014 and 2024.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

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Bibliography

2024

PBTI in Scaled Oxide Submicron Enhancement Mode High-K Gallium Nitride Transistors.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2024

2019

A Statistical Learning Model for Accurate Prediction of Time-Dependent Dielectric Degradation for Low Failure Rates.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2019

2018

Study of dynamic TDDB in scaled FinFET technologies.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2018

2014

A comprehensive modeling framework for gate stack process dependence of DC and AC NBTI in SiON and HKMG p-MOSFETs.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2014

Kaustubh Joshi

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