Ke Wang
Orcid: 0000-0001-7189-9293Affiliations:
- George Washington University, Department of Electrical and Computer Engineering, Washington, DC, USA
According to our database1,
Ke Wang
authored at least 15 papers
between 2019 and 2024.
Collaborative distances:
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Bibliography
2024
Morph-GCNX: A Universal Architecture for High-Performance and Energy-Efficient Graph Convolutional Network Acceleration.
IEEE Trans. Sustain. Comput., 2024
2023
GShuttle: Optimizing Memory Access Efficiency for Graph Convolutional Neural Network Accelerators.
J. Comput. Sci. Technol., February, 2023
Simulation Study of Ferroresonance on Secondary Side of Main Transformer in a 500kV System.
Proceedings of the IEEE Sustainable Power and Energy Conference, 2023
FDMAX: An Elastic Accelerator Architecture for Solving Partial Differential Equations.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023
2022
SecureNoC: A Learning-Enabled, High-Performance, Energy-Efficient, and Secure On-Chip Communication Framework Design.
IEEE Trans. Sustain. Comput., 2022
SGCNAX: A Scalable Graph Convolutional Neural Network Accelerator With Workload Balancing.
IEEE Trans. Parallel Distributed Syst., 2022
Ascend: A Scalable and Energy-Efficient Deep Neural Network Accelerator With Photonic Interconnects.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Proceedings of the IEEE 40th International Conference on Computer Design, 2022
AGAPE: Anomaly Detection with Generative Adversarial Network for Improved Performance, Energy, and Security in Manycore Systems.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
Adapt-NoC: A Flexible Network-on-Chip Design for Heterogeneous Manycore Architectures.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
2020
CURE: A High-Performance, Low-Power, and Reliable Network-on-Chip Design Using Reinforcement Learning.
IEEE Trans. Parallel Distributed Syst., 2020
TSA-NoC: Learning-Based Threat Detection and Mitigation for Secure Network-on-Chip Architecture.
IEEE Micro, 2020
A Versatile and Flexible Chiplet-based System Design for Heterogeneous Manycore Architectures.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
IntelliNoC: a holistic design framework for energy-efficient and reliable on-chip communication for manycores.
Proceedings of the 46th International Symposium on Computer Architecture, 2019
High-performance, Energy-efficient, Fault-tolerant Network-on-Chip Design Using Reinforcement Learnin.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019