Ke Wang
Orcid: 0000-0001-7189-9293Affiliations:
- George Washington University, Department of Electrical and Computer Engineering, Washington, DC, USA
According to our database1,
Ke Wang authored at least 24 papers
between 2019 and 2026.
Collaborative distances:
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Bibliography
2026
Bal-DGCN: A Hardware Acceleration Framework for Balanced Computational Efficiency in DGCNs.
IEEE Trans. Parallel Distributed Syst., June, 2026
2025
HS-GCN: A High-Performance, Sustainable, and Scalable Chiplet-Based Accelerator for Graph Convolutional Network Inference.
IEEE Trans. Sustain. Comput., 2025
FORT-GCN: A Fault-Tolerant and Adaptive Accelerator Design for Efficient Graph Convolutional Network Inference.
ACM Trans. Embed. Comput. Syst., 2025
Learning-Enabled Denial-of-Service (DoS) Attack Detection and Mitigation for Chiplet-Based Hybrid Interconnection Network.
Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025
Algorithmic Strategies for Sustainable Reuse of Neural Network Accelerators with Permanent Faults.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2025
A High-Performance and Flexible Accelerator for Dynamic Graph Convolutional Networks.
Proceedings of the Design, Automation & Test in Europe Conference, 2025
2024
OPT-GCN: A Unified and Scalable Chiplet-Based Accelerator for High-Performance and Energy-Efficient GCN Computation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024
Morph-GCNX: A Universal Architecture for High-Performance and Energy-Efficient Graph Convolutional Network Acceleration.
IEEE Trans. Sustain. Comput., 2024
A Flexible Hybrid Interconnection Design for High-Performance and Energy-Efficient Chiplet-Based Systems.
IEEE Comput. Archit. Lett., 2024
An Efficient Hardware Accelerator Design for Dynamic Graph Convolutional Network (DGCN) Inference.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2023
GShuttle: Optimizing Memory Access Efficiency for Graph Convolutional Neural Network Accelerators.
J. Comput. Sci. Technol., February, 2023
Simulation Study of Ferroresonance on Secondary Side of Main Transformer in a 500kV System.
Proceedings of the IEEE Sustainable Power and Energy Conference, 2023
FDMAX: An Elastic Accelerator Architecture for Solving Partial Differential Equations.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023
2022
SecureNoC: A Learning-Enabled, High-Performance, Energy-Efficient, and Secure On-Chip Communication Framework Design.
IEEE Trans. Sustain. Comput., 2022
SGCNAX: A Scalable Graph Convolutional Neural Network Accelerator With Workload Balancing.
IEEE Trans. Parallel Distributed Syst., 2022
Ascend: A Scalable and Energy-Efficient Deep Neural Network Accelerator With Photonic Interconnects.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Proceedings of the IEEE 40th International Conference on Computer Design, 2022
AGAPE: Anomaly Detection with Generative Adversarial Network for Improved Performance, Energy, and Security in Manycore Systems.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
Adapt-NoC: A Flexible Network-on-Chip Design for Heterogeneous Manycore Architectures.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
2020
CURE: A High-Performance, Low-Power, and Reliable Network-on-Chip Design Using Reinforcement Learning.
IEEE Trans. Parallel Distributed Syst., 2020
TSA-NoC: Learning-Based Threat Detection and Mitigation for Secure Network-on-Chip Architecture.
IEEE Micro, 2020
A Versatile and Flexible Chiplet-based System Design for Heterogeneous Manycore Architectures.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
IntelliNoC: a holistic design framework for energy-efficient and reliable on-chip communication for manycores.
Proceedings of the 46th International Symposium on Computer Architecture, 2019
High-performance, Energy-efficient, Fault-tolerant Network-on-Chip Design Using Reinforcement Learnin.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019