Hao Zheng
Orcid: 0000-0003-4391-2774Affiliations:
- University of Central Florida, Department of Electrical and Computer Engineering, Orlando, FL, USA
- George Washington University, Department of Electrical and Computer Engineering, Washington, DC, USA (former, PhD)
According to our database1,
Hao Zheng
authored at least 22 papers
between 2018 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
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Online presence:
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on orcid.org
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on haozheng.us
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Bibliography
2024
Versa-DNN: A Versatile Architecture Enabling High-Performance and Energy-Efficient Multi-DNN Acceleration.
IEEE Trans. Parallel Distributed Syst., February, 2024
Morph-GCNX: A Universal Architecture for High-Performance and Energy-Efficient Graph Convolutional Network Acceleration.
IEEE Trans. Sustain. Comput., 2024
2023
GShuttle: Optimizing Memory Access Efficiency for Graph Convolutional Neural Network Accelerators.
J. Comput. Sci. Technol., February, 2023
FDMAX: An Elastic Accelerator Architecture for Solving Partial Differential Equations.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023
Polyform: A Versatile Architecture for Multi-DNN Execution via Spatial and Temporal Acceleration.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023
ARIES: Accelerating Distributed Training in Chiplet-Based Systems via Flexible Interconnects.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Path-Based Processing using In-Memory Systolic Arrays for Accelerating Data-Intensive Applications.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
SAGA: Sparsity-Agnostic Graph Convolutional Network Acceleration with Near-Optimal Workload Balance.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Exploring Architecture, Dataflow, and Sparsity for GCN Accelerators: A Holistic Framework.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023
Venus: A Versatile Deep Neural Network Accelerator Architecture Design for Multiple Applications.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
SecureNoC: A Learning-Enabled, High-Performance, Energy-Efficient, and Secure On-Chip Communication Framework Design.
IEEE Trans. Sustain. Comput., 2022
SGCNAX: A Scalable Graph Convolutional Neural Network Accelerator With Workload Balancing.
IEEE Trans. Parallel Distributed Syst., 2022
IEEE Trans. Emerg. Top. Comput., 2022
Ascend: A Scalable and Energy-Efficient Deep Neural Network Accelerator With Photonic Interconnects.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Adapt-Flow: A Flexible DNN Accelerator Architecture for Heterogeneous Dataflow Implementation.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
AGAPE: Anomaly Detection with Generative Adversarial Network for Improved Performance, Energy, and Security in Manycore Systems.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
Adapt-NoC: A Flexible Network-on-Chip Design for Heterogeneous Manycore Architectures.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
2020
TSA-NoC: Learning-Based Threat Detection and Mitigation for Secure Network-on-Chip Architecture.
IEEE Micro, 2020
A Versatile and Flexible Chiplet-based System Design for Heterogeneous Manycore Architectures.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
EZ-Pass: An Energy & Performance-Efficient Power-Gating Router Architecture for Scalable NoCs.
IEEE Comput. Archit. Lett., 2018