Ken Li

Orcid: 0000-0001-5349-4006

According to our database1, Ken Li authored at least 15 papers between 2019 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
A 92.1-dB SNDR Easy-Driving Two-Step NS-SAR-Based Incremental ADC With Concurrent Gain-Error Plus Noise Suppression.
IEEE J. Solid State Circuits, March, 2026

A 95.9-dB SNDR 10-kHz BW Third-Order VCO-Based CT ΔΣ Modulator Using a Phase-Time Two-Step Quantizer.
IEEE J. Solid State Circuits, March, 2026

Hide and Find: A Distributed Adversarial Attack on Federated Graph Learning.
CoRR, March, 2026

2025
PosterCopilot: Toward Layout Reasoning and Controllable Editing for Professional Graphic Design.
CoRR, December, 2025

ALM-PU: positive and unlabeled learning with constrained optimization.
Mach. Learn., September, 2025

VSAGE: An End-to-End Automated VCO-Based ΔΣ ADC Generator.
IEEE Trans. Very Large Scale Integr. Syst., January, 2025

NI-GDBA: Non-Intrusive Distributed Backdoor Attack Based on Adaptive Perturbation on Federated Graph Learning.
Proceedings of the ACM on Web Conference 2025, 2025

A 50-kHz BW 92.1-dB SNDR Incremental ADC Using a Back-End Sampling Two-Step NS-SAR Architecture with Concurrent Gain-Error + Noise Suppression.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

A 95.9-dB SNDR 10-kHz BW 3rd-Order VCO-Based CT ΔΣ Modulator Using a Phase-Time Two-Step Quantizer.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

2024
An 82dB-SNDR Input-Driving-Relaxed Noise-Shaping SAR with Amplifier-Reused In-Loop Buffering and NTF Leakage Reshaping.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023
Blood Glucose Level Prediction: A Graph-based Explainable Method with Federated Learning.
CoRR, 2023

2022
Theoretical total harmonic distortion evaluation based on digital to analogue converter mismatch to improve the linearity of successive approximation register analogue to digital converter.
IET Circuits Devices Syst., 2022

2021
A 10-bit 20-MS/s SAR DAC achieving 57.9-dB SNDR using insensitive geometry DAC array.
Microelectron. J., 2021

2020
A Two-step SAR ADC with Synchronous DEM Calibration Achieving Up to 15% Power Reduction.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020

2019
A Multi-Channel 1.52 µVrms Front End with Orthogonal Frequency Chopping for Neural Recording Applications.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019


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