Shaolan Li

According to our database1, Shaolan Li authored at least 27 papers between 2016 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS.
IEEE J. Solid State Circuits, 2020

A 0.025-mm<sup>2</sup> 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- ΔΣ M Structure.
IEEE J. Solid State Circuits, 2020

An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter.
IEEE J. Solid State Circuits, 2020

An OTA-Less Second-Order VCO-Based CT $\Delta\Sigma$ Modulator Using an Inherent Passive Integrator and Capacitive Feedback.
IEEE J. Solid State Circuits, 2020

A kT/C-Noise-Cancelled Noise-Shaping SAR ADC with a Duty-Cycled Amplifier.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

2019
Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Two-Step ADC With a Continuous-Time SAR-Based First Stage.
IEEE J. Solid State Circuits, 2019

A 0.029-mm<sup>2</sup> 17-fJ/Conversion-Step Third-Order CT ΔΣ ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer.
IEEE J. Solid State Circuits, 2019

Advances in Voltage-Controlled-Oscillator-Based ΔΣ ADCs.
IEICE Trans. Electron., 2019

A 0.6-V Tail-Less Inverter Stacking Amplifier with 0.96 PEF.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 16fJ/Conversion-Step Time-Domain Two-Step Capacitance-to-Digital Converter.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 0.01mm<sup>2</sup> 25µW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Device Layer-Aware Analytical Placement for Analog Circuits.
Proceedings of the 2019 International Symposium on Physical Design, 2019

GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance.
Proceedings of the International Conference on Computer-Aided Design, 2019

MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper.
Proceedings of the International Conference on Computer-Aided Design, 2019

WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A 0.025-mm<sup>2</sup> 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

A 60-fJ/step 11-ENOB VCO-based CTDSM Synthesized from Digital Standard Cell Library.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure.
IEEE J. Solid State Circuits, 2018

A 0.029MM2 17-FJ/Conv.-Step CT $\Delta\Sigma$ ADC with 2<sup>nd</sup>-Order Noise-Shaping SAR Quantizer.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 13-ENOB 2<sup>nd</sup>-order noise-shaping SAR ADC realizing optimized NTF zeros using an error-feedback structure.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Low-power Scaling-friendly Ring Oscillator based ΔΣ ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Second-Order Purely VCO-Based CT Δ∑ ADC Using a Modified DPLL in 40-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
A 174.3-dB FoM VCO-Based CT ΔΣ Modulator With a Fully-Digital Phase Extended Quantizer and Tri-Level Resistor DAC in 130-nm CMOS.
IEEE J. Solid State Circuits, 2017

Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
A 174.3dB FoM VCO-based CT ΔΣ modulator with a fully digital phase extended quantizer and tri-level resistor DAC in 130nm CMOS.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016


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