Shaolan Li

According to our database, Shaolan Li authored at least 42 papers between 2016 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Guest Editorial 2023 Custom Integrated Circuits Conference.

Yan Lu, Shaolan Li

IEEE J. Solid State Circuits, March, 2024

2023

A Systematic and Innovative Six-in-One Evaluation Framework to Drive the Development of Future Hidden Champions.

Dayou Wu, Guochao Peng, Yiwan Ai, Huan Li, Shaolan Li, Yating Peng

Proceedings of the Distributed, Ambient and Pervasive Interactions, 2023

A 1.11 mm² Guidewire IVUS SoC with ±50°-Range Plane Wave Transmit Beamforming.

Xitie Zhang, Evren F. Arkan, Coskun Tekes, Tzuhan Wang, F. Levent Degertekin, Shaolan Li

Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

Enabling Ultra-Low Power Ultrasound Imaging with Compute-in-Memory Sparse Reconstruction Accelerator.

Wantong Li, Xitie Zhang, Junmo Lee, F. Levent Degertekin, Shaolan Li, Shimeng Yu

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023

2022

Design and Optimization of Non-Volatile Capacitive Crossbar Array for In-Memory Computing.

Yuan-Chun Luo, Anni Lu, Jae Hur, Shaolan Li, Shimeng Yu

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques.

Xiyuan Tang, Jiaxin Liu, Yi Shen, Shaolan Li, Linxiao Shen, Arindam Sanyal, Kareem Ragab, Nan Sun

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

An 84-dB-SNDR Low-OSR Fourth-Order Noise-Shaping SAR With an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique.

Tian Xie, Tzu-Han Wang, Zhe Liu, Shaolan Li

IEEE J. Solid State Circuits, 2022

Nonvolatile Capacitive Crossbar Array for In-Memory Computing.

Jae Hur, Yuan-Chun Luo, Anni Lu, Tzu-Han Wang, Shaolan Li, Asif Islam Khan, Shimeng Yu

Adv. Intell. Syst., 2022

An 84dB-SNDR Low-OSR 4^th-Order Noise-Shaping SAR with an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique.

Tzuhan Wang, Tian Xie, Zhe Liu, Shaolan Li

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021

A 13.8-ENOB Fully Dynamic Third-Order Noise-Shaping SAR ADC in a Single-Amplifier EF-CIFF Structure With Hardware-Reusing kT/C Noise Cancellation.

Tzu-Han Wang, Ruowei Wu, Vasu Gupta, Xiyuan Tang, Shaolan Li

IEEE J. Solid State Circuits, 2021

MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII.

Hao Chen, Mingjie Liu, Biying Xu, Keren Zhu, Xiyuan Tang, Shaolan Li, Yibo Lin, Nan Sun, David Z. Pan

IEEE Des. Test, 2021

27.3 A 13.8-ENOB 0.4pF-CIN 3^rd-Order Noise-Shaping SAR in a Single-Amplifier EF-CIFF Structure with Fully Dynamic Hardware-Reusing kT/C Noise Cancelation.

Tzu-Han Wang, Ruowei Wu, Vasu Gupta, Shaolan Li

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Design of Non-volatile Capacitive Crossbar Array for In-Memory Computing.

Yuan-Chun Luo, Anni Lu, Jae Hur, Shaolan Li, Shimeng Yu

Proceedings of the IEEE International Memory Workshop, 2021

An 81.5dB-DR 1.25MHz-BW VCO-Based CT ΔΣ ADC with Double-PFD Quantizer.

Yi Zhong, Xiyuan Tang, Jiaxin Liu, Wenda Zhao, Shaolan Li, Nan Sun

Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020

A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS.

Yi Zhong, Shaolan Li, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Siliang Wu, Nan Sun

IEEE J. Solid State Circuits, 2020

A 0.025-mm² 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- ΔΣ M Structure.

Wenda Zhao, Shaolan Li, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, Nan Sun

IEEE J. Solid State Circuits, 2020

A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier.

Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, Shaolan Li, David Z. Pan, Nan Sun

IEEE J. Solid State Circuits, 2020

An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter.

Xiyuan Tang, Shaolan Li, Xiangxing Yang, Linxiao Shen, Wenda Zhao, Randall P. Williams, Jiaxin Liu, Zhichao Tan, Neal A. Hall, David Z. Pan, Nan Sun

IEEE J. Solid State Circuits, 2020

An OTA-Less Second-Order VCO-Based CT $\Delta\Sigma$ Modulator Using an Inherent Passive Integrator and Capacitive Feedback.

Shaolan Li, David Z. Pan, Nan Sun

IEEE J. Solid State Circuits, 2020

A kT/C-Noise-Cancelled Noise-Shaping SAR ADC with a Duty-Cycled Amplifier.

Shaolan Li

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

2019

Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters.

Jiaxin Liu, Chen-Kai Hsu, Xiyuan Tang, Shaolan Li, Guangjun Wen, Nan Sun

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Two-Step ADC With a Continuous-Time SAR-Based First Stage.

Linxiao Shen, Nan Sun, Yi Shen, Zhelu Li, Wei Shi, Xiyuan Tang, Shaolan Li, Wenda Zhao, Mantian Zhang, Zhangming Zhu

IEEE J. Solid State Circuits, 2019

A 0.029-mm² 17-fJ/Conversion-Step Third-Order CT ΔΣ ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer.

Jiaxin Liu, Shaolan Li, Wenjuan Guo, Guangjun Wen, Nan Sun

IEEE J. Solid State Circuits, 2019

Advances in Voltage-Controlled-Oscillator-Based ΔΣ ADCs.

Shaolan Li, Arindam Sanyal, Kyoungtae Lee, Yeonam Yoon, Xiyuan Tang, Yi Zhong, Kareem Ragab, Nan Sun

IEICE Trans. Electron., 2019

A 0.6-V Tail-Less Inverter Stacking Amplifier with 0.96 PEF.

Linxiao Shen, Abhishek Mukherjee, Shaolan Li, Xiyuan Tang, Nanshu Lu, Nan Sun

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 16fJ/Conversion-Step Time-Domain Two-Step Capacitance-to-Digital Converter.

Xiyuan Tang, Shaolan Li, Linxiao Shen, Wenda Zhao, Xiangxing Yang, Randy Williams, Jiaxin Liu, Zhichao Tan, Neal A. Hall, Nan Sun

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 0.01mm² 25µW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor.

Linxiao Shen, Yi Shen, Xiyuan Tang, Chen-Kai Hsu, Wei Shi, Shaolan Li, Wenda Zhao, Abhishek Mukherjee, Nan Sun

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Device Layer-Aware Analytical Placement for Analog Circuits.

Biying Xu, Shaolan Li, Chak-Wa Pui, Derong Liu, Linxiao Shen, Yibo Lin, Nan Sun, David Z. Pan

Proceedings of the 2019 International Symposium on Physical Design, 2019

GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance.

Keren Zhu, Mingjie Liu, Yibo Lin, Biying Xu, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan

Proceedings of the International Conference on Computer-Aided Design, 2019

MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper.

Biying Xu, Keren Zhu, Mingjie Liu, Yibo Lin, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan

Proceedings of the International Conference on Computer-Aided Design, 2019

WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout.

Biying Xu, Yibo Lin, Xiyuan Tang, Shaolan Li, Linxiao Shen, Nan Sun, David Z. Pan

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A 0.025-mm² 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure.

Shaolan Li, Wenda Zhao, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, Nan Sun

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

A 60-fJ/step 11-ENOB VCO-based CTDSM Synthesized from Digital Standard Cell Library.

Shaolan Li, Biying Xu, David Z. Pan, Nan Sun

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018

A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure.

Shaolan Li, Bo Qiao, Miguel Gandara, David Z. Pan, Nan Sun

IEEE J. Solid State Circuits, 2018

A 0.029MM2 17-FJ/Conv.-Step CT $\Delta\Sigma$ ADC with 2^nd-Order Noise-Shaping SAR Quantizer.

Jiaxin Liu, Shaolan Li, Wenjuan Guo, Guangjun Wen, Nan Sun

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 13-ENOB 2^nd-order noise-shaping SAR ADC realizing optimized NTF zeros using an error-feedback structure.

Shaolan Li, Bo Qiao, Miguel Gandara, Nan Sun

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Low-power Scaling-friendly Ring Oscillator based ΔΣ ADC.

Arindam Sanyal, Shaolan Li, Nan Sun

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Second-Order Purely VCO-Based CT Δ∑ ADC Using a Modified DPLL in 40-nm CMOS.

Yi Zhong, Shaolan Li, Arindam Sanyal, Xiyuan Tang, Linxiao Shen, Siliang Wu, Nan Sun

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017

A 174.3-dB FoM VCO-Based CT ΔΣ Modulator With a Fully-Digital Phase Extended Quantizer and Tri-Level Resistor DAC in 130-nm CMOS.

Shaolan Li, Abhishek Mukherjee, Nan Sun

IEEE J. Solid State Circuits, 2017

Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits.

Biying Xu, Shaolan Li, Xiaoqing Xu, Nan Sun, David Z. Pan

Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology.

Biying Xu, Shaolan Li, Nan Sun, David Z. Pan

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

A 174.3dB FoM VCO-based CT ΔΣ modulator with a fully digital phase extended quantizer and tri-level resistor DAC in 130nm CMOS.

Shaolan Li, Nan Sun

Proceedings of the ESSCIRC Conference 2016: 42^nd European Solid-State Circuits Conference, 2016